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| [ak4683] ms0427-e-02 2007/04 - 1 - general description the ak4683 is a single chip codec that includes two channels of adc and four channels of dac. the adc outputs 24bit data and the dac accepts up to 24bit input data. the adc has the enhanced dual bit architecture with wide dynamic range. the dac introduces the new developed advanced multi-bit architecture, and achieves wider dynamic range and lo wer outband noise. the ak4683 also has digital audio receiver (dir) and transmitter (dit ) compatible with 192khz, 24bits. the dir can automatically detect a non-pcm bit stream such as dolby digital (ac-3)*. the ak4683 has a dynamic range of 100db for adc, 106db for dac and is well suited for digi tal tv and home theater system. * dolby digital (ac-3) is a trademark of dolby laboratories. features ? adc/dac part ? asynchronous adc/dac operation ? 6:1 input selector with pre-amp ? 2ch 24bit adc - 64x oversampling - sampling rate up to 96khz - linear phase digital anti-alias filter - single-ended input - s/(n+d): 90db - dynamic range, s/n: 100db - digital hpf for offset cancellation - channel independent digital volume (+24/-103db, 0.5db/step) - soft mute - overflow flag ? 4ch 24bit dac - 128x oversampling - sampling rate up to 192khz - 24bit 8 times digital filter - single-ended outputs - s/(n+d): 90db - dynamic range, s/n: 106db - channel independent digital volume (+12/-115db, 0.5db/step) - soft mute - de-emphasis filter (32khz, 44.1khz, 48khz) - zero detect function ? stereo headphone amp with volume - 50mw at 16ohm - click-noise free at power on/off ? high jitter tolerance ak4683 asynchronous multi-channel audio codec with dir/t
[ak4683] ms0427-e-02 2007/04 - 2 - ? dir/dit part - aes3, iec60958, s/pdif, eiaj cp1201 compatible - low jitter analog pll - pll lock range : 32khz to 192khz - clock source: pll or x'tal - 4-channel receiver input - 1-channel transmission output (through output or dit) - auxiliary digital input - de-emphasis for 32khz, 44.1khz, 48khz and 96khz - detection functions ? non-pcm bit stream detection ? dts-cd bit stream detection ? sampling frequency detection (32khz, 44.1khz, 48khz, 88.2khz, 96khz, 176.4khz, 192khz) ? unlock & parity error detection ? validity flag detection - up to 24bit audio data format - 40-bit channel status buffer - burst preamble bit pc and pd buffer for non-pcm bit stream - q-subcode buffer for cd bit stream ? ttl level digital i/f ? external master clock input: - 256fs, 384fs, 512fs (fs=32khz 48khz) - 128fs, 192fs, 256fs (fs=64khz 96khz) - 128fs (fs=120khz 192khz) ? master clock output : 128fs/256fs/384fs/512fs ? 2 audio serial i/f (porta, portb) - master/slave mode - i/f format porta: left/right(20/24 bit) justified, i 2 s, tdm portb: left/right(20/24 bit) justified, i 2 s ? 4-wire serial and i 2 c bus p i/f for mode setting ? operating voltage: 4.5 to 5.5v ? power supply for output buffer: 2.7 to 5.5v ? 64pin lqfp package (0.5mm pitch) [ak4683] ms0427-e-02 2007/04 - 3 - block diagram adc audio i/f adc lin1 lin2 lin3 lin4 lin5 lin6 hpf, dvol dac dvol lpf lout1 rout1 lout2 rout2 hpl hpr dac dvol lpf dac dvol lpf dac dvol lpf dac1 audio i/f 4:2 input selector clock recovery x?tal oscillator p i/f xto xti bickb lrckb tx sdtob sdout daif decoder adc dit sdtib rin1 rin2 rin3 rin4 rin5 rin6 ropin risel i2c csn cclk cdti cdto rx0 rx1 rx2 rx3 lisel lopin sdtob0/1 bit dit0/1 bit dit bit mclk2 sdtoa olrcka bicka ilrcka sdtia1 sdtia2 sdtia3 mcko sdtoa0/1 bit dir a dc sdtib sdtia1 through dit rmclk dac10/11/12, dac20/21/22 bit ips0/1, ops0/1 bit lin0/1/2, rin0/1/2 bit dir a dc sdtia1 off dir a dc sdtib off dac2 audio i/f dir a dc sdtib sdtia1 sdtia2 sdtia3 hpf, dvol dir a dc sdtib sdtia1 sdtia2 sdtia3 portb porta [ak4683] ms0427-e-02 2007/04 - 4 - ordering guide ak4683eq -20 +85 c 64pin lqfp (0.5mm pitch) akd4683 evaluation board for ak4683 pin layout pvdd 1 rx0 2 i2c 3 rx1 4 rx2 5 rx3 6 int 7 vout 8 cdto 9 lrckb 10 bickb 11 sdtob 12 olrck a 13 ilrck a 14 bick a 15 sdto a 16 64 r 63 pvss 62 rin6 61 lin6 60 rin5 59 lin5 58 rin4 57 lin4 56 rin3 55 lin3 54 rin2 53 lin2 52 rin1 51 lin1 50 a vdd1 49 17 mcko 18 tvdd 19 dvss 20 dvdd 21 xti 22 xto 23 t x 24 mclk2 25 pdn 26 cdti 27 ccl k 28 csn 29 sdtia1 30 sdtia2 31 sdtia3 32 sdtib risel 48 ropin 47 lopin 46 lisel 45 a vss2 44 a vdd2 43 vcom 42 rout2 41 lout2 40 rout2 39 lout2 38 mutet 37 hpl 36 hpr 35 hvss 34 hvdd 33 a k4683eq top view a vss1 compatibility with ak4588 functions ak4588 ak4683 dac, adc asynchronous operation not available available dac ch# 8ch 4ch hp-amp - 2ch adc input selector - 6:1 [ak4683] ms0427-e-02 2007/04 - 5 - pin/function no. pin name i/o function 1 pvdd - pll power supply pin, 4.5v 5.5v 2 rx0 i receiver channel 0 pin (internal bias ed pin. internally biased at pvdd/2) 3 i2c i control mode select pin. ?l?: 4-wire serial, ?h?: i 2 c bus 4 rx1 i receiver channel 1 pin 5 rx2 i receiver channel 2 pin 6 rx3 i receiver channel 3 pin 7 int o interrupt pin vout o v-bit output pin for receiver input dzf o zero input detect pin when the input data of dac follow total 8192 lrck cycles with ?0? input data, this pin goes to ?h?. and when rstn1 bit is ?0?, pwda bit is ?0?, this pin goes to ?h?. 8 ovf o analog input overflow detect pin this pin goes to ?h? if the analog input of lch or rch overflows. 9 cdto o control data output pin in serial mode and i2c pin = ?l?. 10 lrckb i/o channel clock b pin 11 bickb i/o audio serial data clock b pin 12 sdtob o audio serial data output b pin 13 olrcka i/o output channel clock a pin 14 ilrcka i/o input channel clock a pin 15 bicka i/o audio serial data clock a pin 16 sdtoa o audio serial data output a pin 17 mcko o master clock output pin 18 tvdd - output buffer power supply pin, 2.7v 5.5v 19 dvss - digital ground pin, 0v 20 dvdd - digital power supply pin, 4.5v 5.5v 21 xti i x'tal input pin 22 xto o x'tal output pin 23 tx o transmit channel output pin when dit bit = ?0?, rx0~3 through. when dit bit = ?1?, internal dit output. 24 mclk2 i master clock input pin 25 pdn i power-down mode & reset pin when ?l?, the ak4683 is powered-down, all registers are reset. and then all digital output pins go ?l?. the ak4683 must be reset once upon power-up. cdti i control data input pin in serial mode and i2c pin = ?l?. 26 sda i/o control data pin in serial mode and i2c pin = ?h?. cclk i control data clock pin in serial mode and i2c pin = ?l? 27 scl i control data clock pin in serial mode and i2c pin = ?h? csn i chip select pin in serial mode and i2c pin = ?l?. 28 test i this pin should be connected to dvss in serial mode and i2c pin = ?h?. 29 sdtia1 i audio serial data input a1 pin 30 sdtia2 i audio serial data input a2 pin 31 sdtia3 i audio serial data input a3 pin 32 sdtib i audio serial data input b pin 33 hvdd - hp power supply pin, 4.5v 5.5v 34 hvss - hp ground pin, 0v 35 hpr o hp rch output pin 36 hpl o hp lch output pin 37 mutet - hp common voltage output pin 1 f capacitor should be connect ed to hvss externally. [ak4683] ms0427-e-02 2007/04 - 6 - no. pin name i/o function 38 lout2 o dac2 lch positive analog output pin 39 rout2 o dac2 rch positive analog output pin 40 lout1 o dac1 lch positive analog output pin 41 rout1 o dac1 rch positive analog output pin 42 vcom - dac/adc common voltage output pin 2.2 f capacitor should be connected to avss2 externally. 43 avdd2 - dac power supply pin, 4.5v 5.5v 44 avss2 - dac ground pin, 0v 45 lisel o lch feedback resistor output pin 46 lopin o lch feedback resistor input pin. 0.5 x avdd1. 47 ropin o rch feedback resistor input pin. 0.5 x avdd1. 48 risel o rch feedback resistor output pin 49 avss1 - adc ground pin, 0v 50 avdd1 - adc power supply pin, 4.5v 5.5v 51 lin1 i lch input 1 pin 52 rin1 i rch input 1 pin 53 lin2 i lch input 2 pin 54 rin2 i rch input 2 pin 55 lin3 i lch input 3 pin 56 rin3 i rch input 3 pin 57 lin4 i lch input 4 pin 58 rin4 i rch input 4 pin 59 lin5 i lch input 5 pin 60 rin5 i rch input 5 pin 61 lin6 i lch input 6 pin 62 rin6 i rch input 6 pin 63 pvss - pll ground pin 64 r - external resistor pin 12k +/-1% resistor should be connected to pvss externally. note: all input pins except internal biased pin (rx0) and analog input pins (lin1-6, rin1-6) should not be left floating. handling of unused pin the unused i/o pins should be processed appropriately as below. classification pin name setting analog rx0, lout1-2, rout1-2, lin1-6, rin1-6 these pins should be open. int, xto, mcko, vout/dzf/ovf, sdtoa-b, cdto, tx these pins should be open. digital rx1-3, csn, cclk, cdti, xti, mclk2, olrcka, ilrcka, bicka, sdtia1-3, lrckb, bickb, sdtib these pins should be connected to dvss. [ak4683] ms0427-e-02 2007/04 - 7 - absolute maximum ratings (avss1, avss2, dvss, pvss, hvss=0v; note 1) parameter symbol min max units power supplies adc analog dac analog headphone analog digital pll output buffer |avss2-avss1| ( note 2) |avss2-dvss| ( note 2) |avss2-pvss| ( note 2) |avss2-hvss| ( note 2) avdd1 avdd2 hvdd dvdd pvdd tvdd gnd1 gnd2 gnd3 gnd4 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 - - - - 6.0 6.0 6.0 6.0 6.0 6.0 0.3 0.3 0.3 0.3 v v v v v v v v v v input current (any pins except for supplies) iin - 10 ma analog input voltage (lin, rin pins) vina -0.3 avdd1+0.3 v digital input voltage except for ilrcka, olrcka, lrckb, bicka-b, rx0, i2c pins vind1 -0.3 dvdd+0.3 v ilrcka, olrcka, lrckb, bicka-b pins vind2 -0.3 tvdd+0.3 v rx0, i2cpins vind3 -0.3 pvdd+0.3 v ambient temperature (power applied) ta -20 85 c storage temperature tstg -65 150 c note 1. all voltages with respect to ground. note 2. avss, dvss and pvss must be connected to the same analog ground plane. warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. recommended operating conditions (avss, dvss, pvss=0v; note 3) parameter symbol min typ max units power supplies ( note 4) adc analog dac analog headphone analog digital pll output buffer |dvdd - avdd1| |dvdd - avdd2| |dvdd - hvdd| |dvdd - pvdd| |avdd1 ? avdd2| avdd1 avdd2 hvdd dvdd pvdd tvdd vdd1 vdd2 vdd3 vdd4 vdd5 4.5 4.5 avdd2 4.5 4.5 2.7 -0.3 -0.3 -0.3 -0.3 -0.1 5.0 5.0 5.0 5.0 5.0 5.0 0 0 0 0 0 5.5 5.5 5.5 5.5 5.5 dvdd +0.3 +0.3 +0.3 +0.3 +0.1 v v v v v v v v v v v note 3. all voltages with respect to ground. note 4. the power up sequences among avdd1, avdd2, dvdd , pvdd, hvdd and tv dd are not critical. warning: emd assumes no responsibility for the usage beyond the conditions in this datasheet. [ak4683] ms0427-e-02 2007/04 - 8 - analog characteristics (ta=25 c; avdd1, avdd2, hvdd, dvdd, pvdd, tvdd=5v; avss1, avss2, hvss, dvss, pvss=0v; fs=48khz; bick=64fs; signal frequency=1khz; 24bit data; measurement frequency=20hz 20khz at fs=48khz, 20hz~40khz at fs=96khz; 20hz~40khz at fs=192khz, all blocks are synchronized, unless otherwise specified) parameter min typ max units pre-amp characteristics: feedback resistance 10 50 k s/(n+d) ( note 5) - 100 db s/n (a-weighted) ( note 5) - 108 db load capacitance 20 pf adc analog input characteristics ( note 6) resolution 24 bits s/(n+d) (-0.5dbfs) fs=48khz fs=96khz 84 - 92 86 db db dr (-60dbfs) fs=48khz, a-weighted fs=96khz fs=96khz, a-weighted 92 - - 100 96 100 db db db s/n ( note 7) fs=48khz, a-weighted fs=96khz fs=96khz, a-weighted 92 - - 100 96 100 db db db interchannel isolation ( note 8) 90 105 db interchannel gain mismatch 0.2 0.5 db gain drift 50 - ppm/ c input voltage ( note 6) ain=1.22xavdd1 5.7 6.1 6.5 vpp power supply rejection ( note 9) 50 db dac analog output characteristics resolution 24 bits s/(n+d) fs=48khz fs=96khz fs=192khz 80 - - 90 88 88 db db db dr (-60dbfs) fs=48khz, a-weighted fs=96khz fs=96khz, a-weighted fs=192khz fs=192khz, a-weighted 95 - - - - 106 100 106 100 106 db db db db db s/n ( note 10) fs=48khz, a-weighted fs=96khz fs=96khz, a-weighted fs=192khz fs=192khz, a-weighted 95 - - - - 106 100 106 100 106 db db db db db interchannel isolation 90 110 db interchannel gain mismatch 0.2 0.5 db gain drift 50 - ppm/ c output voltage aout=0.6xavdd2 2.75 3.0 3.25 vpp load resistance (ac load) 5 k load capacitance 30 pf power supply rejection ( note 9) 50 db [ak4683] ms0427-e-02 2007/04 - 9 - analog volume characteristics (opga): step size: +0db -16db -16db -38db -38db -50db 0.1 0.1 - 1 2 4 - - - db db db headphone-amp characteristics: dac hpl/hpr pins, rl=16 output voltage (0.506xhvdd) 1.94 2.43 2.92 vpp s/(n+d) ( ? 3dbfs) - 70 - dbfs s/n (a-weighted) - 90 - db interchannel isolation - 80 - db interchannel gain mismatch - 0.1 0.5 db load resistance 16 - - c1 in figure 1 - - 30 pf load capacitance c2 in figure 1 - - 300 pf power supplies power supply current normal operation (pdn pin = ?h?) ( note 11) avdd1+ avdd2 fs=48khz, fs=96khz fs=192khz hvdd pvdd dvdd+tvdd fs=48khz ( note 12) fs=96khz fs=192khz power-down mode (pdn pin = ?l?) ( note 13) 37 19 7 8 35 45 55 80 52 27 10 11 49 63 77 200 ma ma ma ma ma ma ma a note 5. measured at lisel/risel pins when the input resistor=47kohm, the feedback resistor=24kohm and input level =2vrms. note 6. measured through pre-amp -> adc. input resistor=47kohm, feedback resistor=24kohm. note 7. s/n measured by ccir-arm is 96db(@fs=48khz). note 8. this value is the interchannel isolation between all the channels of the lin1-6 and rin1-6. note 9. psr is applied to avdd, dvdd , pvdd and tvdd with 1khz, 50mvpp. note 10. s/n measured by ccir-arm is 102db(@fs=48khz). note 11. c l =20pf, x'tal=24.576mhz, cm1-0=?10?, cm1-0=?10?, ocks1-0="10"@48khz,"00"@96khz, "11"@192khz. headphone = no output. the resister network is attached to tx pin. note 12. tvdd=6ma(typ@fs=48khz), 7ma(typ@fs=96khz), 10ma(typ@fs=192khz). note 13. in the power-down mode. rx0 input is open and all digital input pins including clock pins (mclk2, bicka, bickb, ilrcka, olrcka, bickb pins ) and rx1-3 pins are held dvss + - + hp-amp 16 hpl, hpr c1 c2 figure 1. headphone amplifier output circuit [ak4683] ms0427-e-02 2007/04 - 10 - filter characteristics (ta=25 c; avdd1, avdd2, dvdd, pvdd, hvdd=4.5 5.5v; tvdd=2.7 5.5v; fs=48khz) parameter symbol min typ max units adc digital filter (decimation lpf): passband ( note 14) 0.1db -0.2db -3.0db pb 0 - - 20.0 23.0 18.9 - - khz khz khz stopband sb 28.0 khz passband ripple pr 0.04 db stopband attenuation sa 68 db group delay ( note 15) gd 19 1/fs group delay distortion gd 0 s adc digital filter (hpf): frequency response ( note 14) -3db -0.1db fr 1.0 6.5 hz hz dac digital filter: passband ( note 14) -0.1db -6.0db pb 0 - 24.0 21.8 - khz khz stopband sb 26.2 khz passband ripple pr 0.02 db stopband attenuation sa 54 db group delay ( note 15) gd 21 1/fs dac digital filter + analog filter: frequency response: 0 20.0khz 40.0khz ( note 16) 80.0khz ( note 16) fr fr fr 0.2 0.3 1.0 db db db note 14. the passband and stopband frequencies are proportional to fs. for example, 21.8khz at ?0.1db is 0.454 x fs (dac). the reference frequency of these responses is 1khz. note 15. the calculating delay time which occurred by digi tal filtering. this time is from setting the input of analog signal to setting the 24bit data of both channels to the output register of porta or portb. for dac, this time is from setting the 20/24bit data of bo th channels on input register of porta or portb to the output of analog signal. note 16. 40khz@fs=96khz, 80khz@fs=192khz [ak4683] ms0427-e-02 2007/04 - 11 - dc characteristics (ta=25 c; avdd1, avdd2, dvdd, pvdd, hvdd=4.5 5.5v; tvdd=2.7 5.5v) parameter symbol min typ max units high-level input voltage (except xti pin) (xti pin) low-level input voltage (except xti pin) (xti pin) vih vih vil vil 2.2 70%dvdd - - - - - - - - 0.8 30%dvdd v v v v input voltage at ac coupling (xti pin) ( note 17) vac 40%dvdd - - vpp high-level output voltage (except tx pins: iout=-400 a) (tx pin: iout=-400 a) low-level output voltage (iout=400 a) voh voh vol tvdd-0.4 dvdd-0.4 - - - - - 0.4 v v v input leakage curren t (except rx0 pin) iin - - 10 a note 17. in case of connectin g capacitance to xti pin. s/pdif receiver characteristics (rx0) (ta=25 c; avdd1, avdd2, dvdd, pvdd, hvdd=4.5 5.5v; tvdd=2.7 5.5v) parameter symbol min typ max units input resistance zin 10 k input voltage (internally biased at pvdd/2) vth 200 mvpp input hysteresis vhy - 50 mv input sample frequency fs 32 - 192 khz vcom pvdd pvss rx0 pin 20k(typ) 20k(typ) internal biased pin circuit s/pdif receiver characteristics (rx1-3) (ta=25 c; avdd1, avdd2, dvdd, pvdd, hvdd=4.5~5.5v;tvdd=2.7~5.5v) parameter symbol min typ max units high-level input voltage low-level input voltage vih vil 2.2 - - - 0.8 v v input sample frequency fs 32 - 192 khz input leakage current iin - - 10 a [ak4683] ms0427-e-02 2007/04 - 12 - switching characteristics (ta=25 c; avdd1, avdd2, dvdd, pvdd, hvdd=4.5 5.5v; tvdd=2.7 5.5v; c l =20pf; note 18) parameter symbol min typ max units master clock timing crystal resonator frequency fxtal 11.2896 24.576 mhz external clock frequency duty feclk declk 4.096 40 50 24.576 60 mhz % mcko output frequency duty ( note 19) ( note 20) fmck dmclk dmck 4.096 40 50 33 24.576 60 mhz % % pll clock recover frequency (rx0-3) fpll 32 - 192 khz master clock 256fsn, 128fsd: pulse width low pulse width high 384fsn, 192fsd: pulse width low pulse width high 512fsn, 256fsd, 128fsq: pulse width low pulse width high fclk tclkl tclkh fclk tclkl tclkh fclk tclkl tclkh 8.192 27 27 12.288 20 20 16.384 15 15 12.288 18.432 24.576 mhz ns ns mhz ns ns mhz ns ns lrcka (lrckb) timing (slave mode) normal mode normal speed mode double speed mode quad speed mode duty cycle fsn fsd fsq duty 32 64 120 45 48 96 192 55 khz khz khz % tdm 256 mode lrcka frequency ?h? time ?l? time fsd tlrh tlrl 32 1/256fs 1/256fs 48 khz ns ns tdm 128 mode lrcka frequency ?h? time ?l? time fsd tlrh tlrl 64 1/128fs 1/128fs 96 khz ns ns lrcka (lrckb) timing (master mode) normal mode normal speed mode double speed mode quad speed mode duty cycle fsn fsd fsq duty 32 64 120 50 48 96 192 khz khz khz % tdm 256 mode lrcka frequency ?h? time ( note 21) fsn tlrh 32 1/8fs 48 khz ns tdm 128 mode lrcka frequency ?h? time ( note 21) fsd tlrh 64 1/4fs 96 khz ns power-down & reset timing pdn pulse width ( note 22) pdn ? ? to sdto valid ( note 23) tpd tpdv 150 522 ns 1/fs note 18. sdtoa is specified against olrcka, sdtia1-3 are measured against ilrcka. note 19. when mcko1-0 bits = ?01?, ?10? or mcko1-0 bits = ?00? and cksdt bit = ?0?. note 20. when mcko1-0 bits = ?00? and cksdt bit = ?1? and the extclk is selected by cm1-0 bits. duty = (?h? width) / (clock cycle) x 100 note 21. ?l? time at i 2 s format note 22. the ak4683 can be reset by bringing pdn ?l? to ?h? upon power-up. note 23. these cycles are the number of lrcka (lrckb) rising from pdn rising. [ak4683] ms0427-e-02 2007/04 - 13 - parameter symbol min typ max units audio interface timing (slave mode) normal mode bicka (bickb) period bicka (bickb) pulse width low pulse width high lrcka (lrckb) edge to bicka (bickb) ? ? ( note 24) bicka (bickb) ? ? to lrcka (lrckb) edge ( note 24) lrcka (lrckb) to sdtoa, sdtob (msb) bicka (bickb) ? ? to sdtoa, sdtob sdtia1-3, sdtib hold time sdtia1-3, sdtib setup time tbck tbckl tbckh tlrb tblr tlrs tbsd tsdh tsds 81 32 32 20 20 20 20 20 20 ns ns ns ns ns ns ns ns ns tdm 256 mode bicka period bicka pulse width low pulse width high lrcka edge to bicka ? ? ( note 24) bicka ? ? to lrcka edge ( note 24) bicka ? ? to sdtoa sdtia1 hold time sdtia1 setup time tbck tbckl tbckh tlrb tblr tbsd tsdh tsds 81 32 32 20 20 10 10 20 ns ns ns ns ns ns ns ns tdm 128 mode bicka period bicka pulse width low pulse width high lrcka edge to bicka ? ? ( note 24) bicka ? ? to lrcka edge ( note 24) bicka ? ? to sdtoa sdtia1-2 hold time sdtia1-2 setup time tbck tbckl tbckh tlrb tblr tbsd tsdh tsds 81 32 32 20 20 10 10 20 ns ns ns ns ns ns ns ns audio interface timi ng (master mode) normal mode bicka (bickb) frequency bicka (bickb) duty bicka (bickb) ? ? to lrcka (lrckb) edge bicka (bickb)? ? to sdto sdtia1-3, b hold time sdtia1-3, b setup time fbck dbck tmblr tbsd tsdh tsds -20 20 20 64fs 50 20 20 hz % ns ns ns ns tdm 256 mode bicka frequency bicka duty ( note 25) bicka ? ? to lrcka edge bicka ? ? to sdtoa sdtia1 hold time sdtia1 setup time fbck dbck tmblr tbsd tsdh tsds -12 10 10 256fs 50 12 20 hz % ns ns ns ns tdm 128 mode bicka frequency bicka duty ( note 26) bicka ? ? to lrcka edge bicka ? ? to sdtoa sdtia1-2 hold time sdtia1-2 setup time fbck dbck tmblr tbsd tsdh tsds -12 10 10 128fs 50 12 20 hz % ns ns ns ns note 24. bick rising edge must not occur at the same time as lrck edge. note 25. when mclk2/xti is 512fs, dbck is guaranteed. when 384fs and 256fs, dbck can not be guaranteed. note 26. when mclk2/xti is 256fs, dbck is guaranteed. when 128fs, dbck can not be guaranteed. [ak4683] ms0427-e-02 2007/04 - 14 - parameter symbol min typ max units control interface timing (4-wire serial mode) cclk period cclk pulse width low pulse width high cdti setup time cdti hold time csn ?h? time csn ? ? to cclk ? ? cclk ? ? to csn ? ? cdto delay csn ? ? to cdto hi-z tcck tcckl tcckh tcds tcdh tcsw tcss tcsh tdcd tccz 200 80 80 50 50 150 50 50 45 70 ns ns ns ns ns ns ns ns ns ns control interface timing (i 2 c bus mode) scl clock frequency bus free time between transmissions start condition hold time (prior to first clock pulse) clock low time clock high time setup time for repeated start condition sda hold time from scl falling ( note 27) sda setup time from scl rising rise time of both sda and scl lines fall time of both sda and scl lines setup time for stop condition pulse width of spike noise suppressed by input filter capacitive load on bus fscl tbuf thd:sta tlow thigh tsu:sta thd:dat tsu:dat tr tf tsu:sto tsp cb - 4.7 4.0 4.7 4.0 4.7 0 0.25 - - 4.0 0 - 100 - - - - - - - 1.0 0.3 - 50 400 khz s s s s s s s s s s ns pf note 27. data must be held for sufficient time to bridge the 300 ns transition time of scl. note 28. i 2 c is a registered trademark of philips semiconductors. [ak4683] ms0427-e-02 2007/04 - 15 - timing diagram 1/fclk tclkl vih tclkh mclk vil 1/fsn, 1/fsd, 1/fsq lrck vih vil tbck tbckl vih tbckh bick vil clock timing (normal mode) 1/fclk tclkl vih tclkh mclk vil 1/fsn, 1/fsd lrck vih vil tlrl tlrh tbck tbckl vih tbckh bick vil clock timing (tdm 256 mode, tdm 128 mode) lrck= lrckb, ilrcka, olrcka, bick= bicka, bickb, sdti= sdtia, sdtib, sdto= sdtoa, sdtob. [ak4683] ms0427-e-02 2007/04 - 16 - tlrb lrck vih bick vil tlrs sdto 50%tvdd tbsd vih vil tblr tsds sdti vih vil tsdh audio interface timing (normal mode) tlrb lrck vih bick vil sdto 50%tvdd tbsd vih vil tblr tsds sdti vih vil tsdh audio interface timing (tdm 256 mode, tdm 128 mode) [ak4683] ms0427-e-02 2007/04 - 17 - lrck bick sdto tbsd tmblr 50%tvdd 50%tvdd 50%tvdd sdti tdxh tdxs vih vil audio interface timing (master mode) tpd pdn vil power down & reset timing [ak4683] ms0427-e-02 2007/04 - 18 - tcckl csn cclk tcds cdti tcdh tcss c0 a4 tcckh cdto hi-z r/w c1 vih vil vih vil vih vil tcck write/read command input timing in 4-wire serial mode the adc/dac part doesn?t support read command. tcsw csn cclk cdti d2 d0 tcsh cdto hi-z d1 d3 vih vil vih vil vih vil write data input timing in 4-wire serial mode csn cclk tdcd cdto d7 d6 cdti a1 a0 d5 hi-z 50%tvdd vih vil vih vil vih vil read data output timing 1 in 4-wire serial mode the adc/dac part doesn? t support read command.. [ak4683] ms0427-e-02 2007/04 - 19 - csn cclk tccz cdto d2 d1 cdti d0 d3 tcsw tcsh 50%tvdd vih vil vih vil vih vil hi-z read data input timing 2 in 4-wire serial mode the adc/dac part doesn?t support read command. thigh scl sda vih tlow tbuf thd:sta tr tf thd:dat tsu:dat tsu:sta stop start start stop tsu:sto vil vih vil tsp i 2 c bus mode timing the adc/dac part doesn? t support read command. tpd vil pdn tpdv sdto 50%tvdd vih power-down & reset timing [ak4683] ms0427-e-02 2007/04 - 20 - operation overview (general) device configuration and system clocks the ak4683 integrates th e stereo adc with input selector, 4ch dac w ith stereo hp amp, dir and dit. the ak4683 has two serial audio interfaces (porta , b) for two input/output dataset ( figure 2). each block can independently select the operation clock from the three clock sources (recovered clock from dir (rmclk), x?tal clock (xti) and external clock (mclk2)) and also input data source/output data destination. by using the clock gen c, the loop-back such as ad-da can operate even if th e porta/b are powered down. porta clock gen a x?tal oscillator (xti) mcko dir xti mclk2 dir mclk2 dir xti mclk2 adc dac dit note clkb0/1 bit clka0/1 bit mcko0/1 bit dir xti mclk2 clock gen c dir xti mclk2 clkl0/1 bit portb clock gen b dir xti mclk2 dir xti mclk2 dir xti mclk2 figure 2 system clock note: each block must select the same clock source each other when connected. the operation will not be normal when the clock sources are not same among a connection. the adc and dac are synchronized to the clock source that the connected block uses. even if the rmclk is select ed, the x?tal/mclk2 may be chosen by the setting of cm1-0bits. dir and dit must be synchronized when these two blocks operates. [ak4683] ms0427-e-02 2007/04 - 21 - x?tal oscillator the following circuits are available to feed the clock to xti pin of the ak4683. 1) x?tal xti xto ak4683 25k c c (typ) note: external capacitance depends on the crystal oscillator (typ. 10-40pf) figure 3. x?tal mode 2) external clock - note: input clock must not exceed dvdd. xti xto ak4683 25k external clock (typ) xti xto ak4683 25k external clock c (typ) (input: cmos level) (input: 40%dvdd, c=0.1 f) figure 4 dc-coupled input figure 5 ac-coupled input 3) xti/xto are not used xti xto ak4683 25k (typ) figure 6. off mode [ak4683] ms0427-e-02 2007/04 - 22 - master clock output the ak4683 has one master clock output pin. the clock sour ce can be selected from the three clocks (recovered clock from dir (rmclk), x?tal clock (xti) and external clock (mclk2)). when the dir is powered-down or unlocked state at cm1/0 bit = ?10?, the clkdt bit selects the clock source. the ocks1/0 bits select the clock speed. the 512fs at fs=96khz, 256fs/512fs at fs=192khz are not available. cm1 bit cm0 bit unlock clock source 0 0 - rmclk 0 1 - extclk 0 rmclk 1 0 1 extclk 1 1 - extclk table 1. clock mode control clkdt bit clock source 0 xti default 1 mclk2 table 2. extclk control ocks1 bit ocks0 bit mclko(rmclk) fs (max) 0 0 256fs 96 khz 0 1 256fs 96 khz 1 0 512fs 48 khz 1 1 128fs 192 khz table 3. mclko speed mcko1 bit mcko0 bit mcko clock source 0 0 dir 0 1 x?tal(xti) default 1 0 mclk2 1 1 reserved table 4. mcko clock source control x?tal oscillator (xti) mcko pll mclk2 mcko0/1 bit dir xti mclk2 cksdt bit x2/3 cm0/1 bit clkdt bit ocks1/0 bit rmclk extclk figure 7. mcko clock [ak4683] ms0427-e-02 2007/04 - 23 - master/slave mode change msa and msb bits control the master/slave mode of port a and portb respectively. the ?1? is for master mode, ?0? is for slave mode. the ak4683 is slave mode at power- down (pdn pin = ?l?). to change to the master mode, write ?1? to msa/msb bit. the acksai, acksao and acks b bits are ignored in master mode. until when writing ?1? to msa/msb bit, the ilrcka, olrcka, bicka, l rckb and bickb pin are input pins. pull-up(or down) resistor with around 100kohm is required to prevent the floating of these input pins. msa, msb bit mode 0 slave mode (default) 1 master mode table 5. select master/salve mode note: when porta and portb operate synchronously, portb must not be the master mode. in that case the porta must be the master mode, or both porta and portb must be the slave mode with supplying the same bick and lrck. other detection function the func1-0 bit selects the function of vout / dzf / ovf pin. mode func1 func0 mode 0 0 0 off (?l?) 1 0 1 adc overflow detection 2 1 0 dac zero detection 3 1 1 v bit output default table 6. detection function control 1. overflow detection the ak4683 has overflow detect function for analog input. ovf pin goes to ?h? if analog input of lch or rch overflows (more than -0.3dbfs). ovf output for overflowed analog input has the same group delay as adc (gd = 16/fs = 333 s @fs=48khz). ovf pin is ?l? for 522/fs (=10.9ms @fs=48khz) after pdn = ? ?, and then overflow detection is enabled. the overflow detection is applied to the data between the digital hpf and the datt. [ak4683] ms0427-e-02 2007/04 - 24 - 2. zero detection the ak4683 has one pin for zero detect flag output . the dzfm1-0 bits select the channel grouping ( table 7). the dzf pin goes ?h? when all of the enabled channels are con tinuously zeros for 8192 lrck cycles. dzf pin immediately goes to ?l? if input data of any enabled channel is not zero after going dzf ?h?. aout mode dzfm1 bit dzfm0 bit l1 r1 l2 r2 0 0 0 enable enable enable enable (default) 1 0 1 enable enable - - 2 1 0 - - enable enable 3 1 1 - - - - table 7. zero detection control 3. validity detection the ak4683 has validity detection function. dir decodes the v bit and output ?h? via pin. when unlocked, ?l? is output. [ak4683] ms0427-e-02 2007/04 - 25 - operation overview (adc/dac/porta, b part) system clock the ak4683 has two audio serial interface (porta, b), ca n operate these ports with asynchronous. at each port, the external clocks, which are required to operate the ak4683, are mclk, lrck and bick. the mclk should be synchronized with lrck but the phase is not critical. the clka1-0, clkb1-0bits select th e clock sources for each port ( table 8, table 9). the msa and msb bits select the master/slave mode ( table 16, table 17). the block that is connected to porta/b and the block that is connected to the port indirectly operate at the same clock as the porta/b selects. e. g. when the dac select s the adc data while the portb selects the adc data also, the dac operates same clock as the portb selects. the bl ock that isn?t connected to porta/b is automatically connected to the clock gen c and operates the same cloc k as the clock gen c selects with the clkl1-0 bits ( table 10). in master mode, the cksia2-0, olra1-0, bickaf, cksb2-0 bits select the clock frequency ( table 11, table 12 , table 13, table 14). in master mode, external clock (mclk) should always be supplied except in the power-down mode. the ak4683 is in power-down mode until mclk will be supplied, when reset was canceled by power-on and so on. at porta, the input/output data has independent lrck (ilrcka/olrcka) and common bick (bicka). the ilrck and olrck can operate at different sample rate but synchronized each other ( table 12). in slave mode, external clocks (mclk, bick, lrck) should always be present whenever the ak4683 is in normal operation mode (pdn pin = ?h?). the master clock (mclk) should be synchronized with lrck but the phase is not critical. if these clocks are not provided, the ak4683 ma y draw excess current because the device utilizes dynamic refreshed logic internally. if the external clocks are not present, the ak4683 should be in the power-down mode (pdn pin = ?l?) or in the reset mode (rstn1 bit = ?0?). af ter exiting reset at power-up etc., the ak4683 is in the power-down mode until mclk and lrck are input. when the block selects rmclk as clock source, the sample rate of the port in the master mode or adc/dac connecting to the clock gen c is forced to the same rate as dir. the dfsad, dfsda1-0 bits should be controlled properly. note: when porta and portb operate synchronously, por tb must not be the in master mode. in that case the porta must be in the master mode, or both porta and portb must be in the slave mode with supplying the same bick and lrck. [ak4683] ms0427-e-02 2007/04 - 26 - clka1 bit clka0 bit porta clock source 0 0 dir 0 1 x?tal(xti) (default) 1 0 mclk2 1 1 reserved table 8. porta clock source control clkb1 bit clkb0 bit portb clock source 0 0 dir 0 1 x?tal(xti) (default) 1 0 mclk2 1 1 reserved table 9. portb clock source control clkl1 bit clkl0 bit clock gen c clock source 0 0 dir 0 1 x?tal (xti) (default) 1 0 mclk2 1 1 reserved table 10. clock gen c clock source control cksai2 cksai1 cksai0 clock speed 0 0 0 128fs 0 0 1 192fs 0 1 0 256fs (default) 0 1 1 384fs 1 0 0 512fs 1 0 1 reserved 1 1 0 reserved 1 1 1 reserved table 11. porta input data clock control (master mode) olra1 bit olra0 bit olrcka clock freq 0 0 ilrcka x 1 (default) 0 1 ilrcka x 1/2 1 0 ilrcka x 2 1 1 reserved note: select olra1-0 bits = ?00? in tdm mode. table 12. porta output data control (master mode) [ak4683] ms0427-e-02 2007/04 - 27 - bcaf bit porta bick frequency mode 0 ilrck x 64 (default) 1 ilrck x128 note: ilrck x 128 is available when the mclk=ilrck x 256 or higher. bcaf bit is ignored in tdm mode. table 13. porta bick control (master mode) cksb2 cksb1 cksb0 clock speed 0 0 0 128fs 0 0 1 192fs 0 1 0 256fs (default) 0 1 1 384fs 1 0 0 512fs 1 0 1 reserved 1 1 0 reserved 1 1 1 reserved table 14. portb data clock control (master mode) cksl2 cksl1 cksl0 clock speed 0 0 0 128fs 0 0 1 192fs 0 1 0 256fs (default) 0 1 1 384fs 1 0 0 512fs 1 0 1 reserved 1 1 0 reserved 1 1 1 reserved table 15. clock gen c clock control in master mode, lrcka (lrckb) pin, bicka (bickb) pin are output pins. in slave mode, these are input pins ( table 18). msa bit porta master/slave mode 0 slave (default) 1 master table 16. porta master/slave control msb bit portb master/slave mode 0 slave (default) 1 master table 17. portb master/slave control [ak4683] ms0427-e-02 2007/04 - 28 - pdn pin pwpoa(pwpob) bit master/slave lrcka (lrckb) pin bicka (bickb) pin l - slave input input slave input (*) input (*) h ?0? master ?l? output l l? output slave input input h ?1? master output output (*): these are input pins, but input signals are ignored internally. table 18. lrcka (lrckb) pin, bicka (bickb) pin the sdtob1-0, sdtoa1-0 bits select the output data source of each port. sdtoa1 bit sdtoa0 bit sdtoa source 0 0 dir 0 1 adc (default) 1 0 sdtib 1 1 off (?l? output) table 19. sdtoa source control sdtob1 bit sdtob0 bit sdtob source 0 0 dir 0 1 adc (default) 1 0 off 1 1 sdtia1 table 20. sdtob source control [ak4683] ms0427-e-02 2007/04 - 29 - adc, dac control there are two modes for controlling the sampling speed fo r adc and dac. one is the manual setting mode using the dfsad1-0, dfsda1-0 bits, and the other is auto setting mode. when the block connects to both porta and portb, the porta setting is used. 1. manual setting mode (acska d / acskda bit = ?0?: default) when the adc and dac are connected to each port placed in manual setting mode, the sampling speed are selected by dfsad, dfsda1-0 bits ( table 21, table 22). the frequencies and the duties of the clocks (ilrcka, olrcka, lrckb, bicka, bickb) may be unstable for the moment when changing the sampling speed mode. dfsad0 sampling speed (fs) 0 normal speed mode 32khz~48khz (default) 1 double speed mode 64khz~96khz table 21.adc sampling speed (manual setting mode) dfsda1 dfsda0 sampling speed (fs) 0 0 normal speed mode 32khz~48khz 0 1 double speed mode 64khz~96khz (default) 1 0 quad speed mode 120khz~192khz 1 1 not available - table 22.dac sampling speed (manual setting mode) lrcka (lrckb) mclk (mhz) bicka (bickb) (mhz) fs 256fs 384fs 512fs 64fs 32.0khz 8.1920 12.2880 16.3840 2.0480 44.1khz 11.2896 16.9344 22.5792 2.8224 48.0khz 12.2880 18.4320 24.5760 3.0720 (normal speed mode @manual setting mode) table 23. system clock example lrcka (lrckb) mclk (mhz) bicka (bickb) (mhz) fs 128fs 192fs 256fs 64fs 88.2khz 11.2896 16.9344 22.5792 5.6448 96.0khz 12.2880 18.4320 24.5760 6.1440 (double speed mode @manual setting mode) (note: adc is not available for 128fs and 192fs at double speed mode (dfsad=?1?)) table 24. system clock example [ak4683] ms0427-e-02 2007/04 - 30 - lrcka (lrckb) mclk (mhz) bicka (bickb) (mhz) fs 128fs 192fs 256fs 64fs 176.4khz 22.5792 - - 11.2896 192.0khz 24.5760 - - 12.2880 (quad speed mode @manual setting mode) (note: adc is not available at the quad speed mode) table 25. system clock example 2. auto setting mode (acskad/acskda bit = ?1?) when the adc and dacs are connected to each port pla ced in auto setting mode, mclk frequency is detected automatically ( table 26) and the internal master cloc k is set to the appropriate frequency ( table 27). in this mode, the setting of dfsad, dfsda1-0 bits are ignored. mclk sampling speed 512fs normal 256fs double 128fs quad table 26. sampling speed (auto setting mode) lrcka (lrckb) mclk (mhz) fs 128fs 256fs 512fs sampling speed 32.0khz - - 16.3840 44.1khz - - 22.5792 48.0khz - - 24.5760 normal 88.2khz - 22.5792 - 96.0khz - 24.5760 - double 176.4khz 22.5792 - - 192.0khz 24.5760 - - quad table 27. system clock example (auto setting mode) [ak4683] ms0427-e-02 2007/04 - 31 - the dac12-10, dac22-20 bits select the output data for each dac. dac1 and dac2 must be connected to the same port. dac12 bit dac11 bit dac10 bit dac1 source 0 0 0 dir 0 0 1 adc 0 1 0 sdtib 0 1 1 sdtia1 (default) 1 0 0 sdtia2 1 0 1 sdtia3 1 1 0 reserved 1 1 1 reserved table 28. dac1 source control dac22 bit dac21 bit dac20 bit dac2 source 0 0 0 dir 0 0 1 adc 0 1 0 sdtib 0 1 1 sdtia1 1 0 0 sdtia2 (default) 1 0 1 sdtia3 1 1 0 reserved 1 1 1 reserved table 29. dac2 source control [ak4683] ms0427-e-02 2007/04 - 32 - de-emphasis filter the ak4683 includes the digital de-emphasis filter (tc=50/15 s) by iir filter. de-emphasis filter is not available in double speed mode and quad speed mode. this filter corre sponds to three sampling frequencies (32khz, 44.1khz, 48khz). de-emphasis of each dac can be set individually by register. mode sampling speed dem1 dem0 dem 0 normal speed 0 0 44.1khz 1 normal speed 0 1 off 2 normal speed 1 0 48khz 3 normal speed 1 1 32khz (default) table 30. de-emphasis control digital high pass filter the adc has a digital high pass filter for dc offset cancel. the cut-off frequency of the hp f is 1.0hz at fs=48khz and scales with sampling rate (fs). audio serial interface format each porta/b can select independent au dio interface format. the tdma1-0, difa1-0 bits control the audio format for porta and support normal mode, tdm256 mode and tdm128 mode. the difb1-0 bits control the audio format for portb and support only normal mode. the default is mode 2. in all modes the serial data is msb-first, 2?s complement format. the sdto pins are clocked out on the falling edge of bick pins and the sdti pins are latched on the rising edge of bick pins. 1. setting for the porta 1-1. normal mode: tdma1-0 bit = ?00? the tdma1-0 bits = ?00? set the ak4683 audio serial interface format to the normal mode. the difa1-0 bits select following eight serial data format ( table 31). lrcka bicka mode master /slave difa1 difa0 sdtoa sdtia1-3 i/o i/o 0 slave 0 0 24bit, l j 20bit, r j h/l i 48fs i 1 slave 0 1 24bit, l j 24bit, r j h/l i 48fs i 2 slave 1 0 24bit, l j 24bit, l j h/l i 48fs i (default) 3 slave 1 1 24bit, i 2 s 24bit, i 2 s l/h i 48fs i 4 master 0 0 24bit, l j 20bit, r j h/l o 64fs o 5 master 0 1 24bit, l j 24bit, r j h/l o 64fs o 6 master 1 0 24bit, l j 24bit, l j h/l o 64fs o 7 master 1 1 24bit, i 2 s 24bit, i 2 s l/h o 64fs o table 31 audio interface format (normal mode, l j: left justified, r j: right justified.) [ak4683] ms0427-e-02 2007/04 - 33 - 1-2. tdm 256 mode: tdma1-0 bit = ?01? the tdma1-0 bits = ?01? set the ak4683 audio serial interface format to the tdm 256 mode. the serial data of all sdtia (1,2,3) is input to the sdtia1 pin. the input data to sdtia2-3 pins is ignored. bicka should be fixed to 256fs. ?h? time and ?l? time of i/olrcka pin should be 1/256fs at least. the difa1-0 bits select eight modes. lrcka bicka mode master /slave difa1 difa0 sdtoa sdtia1-3 i/o i/o 8 slave 0 0 24bit, l j 20bit, r j i 256fs i 9 slave 0 1 24bit, l j 24bit, r j i 256fs i 10 slave 1 0 24bit, l j 24bit, l j i 256fs i (default) 11 slave 1 1 24bit, i 2 s 24bit, i 2 s i 256fs i 12 master 0 0 24bit, l j 20bit, r j o 256fs o 13 master 0 1 24bit, l j 24bit, r j o 256fs o 14 master 1 0 24bit, l j 24bit, l j o 256fs o 15 master 1 1 24bit, i 2 s 24bit, i 2 s o 256fs o table 32. audio interface format (tdm 256 mode, l j: left jus tified, r j: right justified.) 1-3. tdm 128 mode: tdma1-0 bit = ?11? the tdma1-0 bits = ?11? set the ak4683 audio serial in terface format to the tdm 1 286 mode. the four channel serial data (sdtia1, 2) is input to the sdtia1 pin. othe r two channel data (sdtia3) is input to the sdtia2 pin. lrcka bicka mode master /slave difa1 difa0 sdtoa sdtia1-3 i/o i/o 16 slave 0 0 24bit, l j 20bit, r j i 128fs i 17 slave 0 1 24bit, l j 24bit, r j i 128fs i 18 slave 1 0 24bit, l j 24bit, l j i 128fs i (default) 19 slave 1 1 24bit, i 2 s 24bit, i 2 s i 128fs i 20 master 0 0 24bit, l j 20bit, r j o 128fs o 21 master 0 1 24bit, l j 24bit, r j o 128fs o 22 master 1 0 24bit, l j 24bit, l j o 128fs o 23 master 1 1 24bit, i 2 s 24bit, i 2 s o 128fs o table 33. audio interface format (tdm 128 mode, l j: left jus tified, r j: right justified.) [ak4683] ms0427-e-02 2007/04 - 34 - 2. setting for the portb 2-1: normal mode: the portb supports only the normal mode. the difb1-0 bits select following eight serial data format ( table 34). lrckb bickb mode master /slave difb1 difb0 sdtob sdtib i/o i/o 0 slave 0 0 24bit, l j 20bit, r j h/l i 48fs i 1 slave 0 1 24bit, l j 24bit, r j h/l i 48fs i 2 slave 1 0 24bit, l j 24bit, l j h/l i 48fs i (default) 3 slave 1 1 24bit, i 2 s 24bit, i 2 s l/h i 48fs i 4 master 0 0 24bit, l j 20bit, r j h/l o 64fs o 5 master 0 1 24bit, l j 24bit, r j h/l o 64fs o 6 master 1 0 24bit, l j 24bit, l j h/l o 64fs o 7 master 1 1 24bit, i 2 s 24bit, i 2 s l/h o 64fs o table 34. audio interface format (normal mode, l j: left justified, r j: right justified.) lrck bick(64fs) sdto(o) 0 1 2 12 13 14 24 25 31 0 1 2 12 13 14 24 25 31 0 23 1 22 0 23 22 12 11 10 0 23 sdti(i) 1 18 0 19 8 7 1 18 0 19 8 7 lch data rch data don?t care don?t care 12 11 10 sdto-23:msb, 0:lsb; sdti-19:msb, 0:lsb figure 8. mode 0,4 timing lrck bick(64fs) sdto(o) 0 1 2 8 9 10 24 25 31 0 1 2 8 9 10 24 25 31 0 23 1 22 0 23 22 16 15 14 0 23 sdti(i) 1 22 0 23 8 7 1 22 0 23 8 7 23:msb, 0:lsb lch data rch data don?t care don?t care 16 15 14 figure 9. mode 1 ,5 timing lrck bick(64fs) sdto(o) 0 1 2 21 22 23 24 31 0 1 2 0 23 1 22 1 23 22 23 sdti(i) 22 23 0 22 23 23:msb, 0:lsb lch data rch data don?t care 2 2 1 28 29 30 23 0 22 23 24 31 1 0 don?t care 2 21 28 29 30 0 figure 10.mode 2,6 timing [ak4683] ms0427-e-02 2007/04 - 35 - lrck bick(64fs) sdto(o) 0 1 2 3 22 23 24 25 0 0 1 sdti(i) 31 29 30 23 22 1 22 23 0 23:msb, 0:lsb lch data rch data don?t care 2 2 1 0 2 3 22 23 24 25 0 31 29 30 23 22 1 22 23 0 don?t care 2 21 0 1 figure 11. mode 3 ,7 timing 256 bick bicka(256fs) sdtoa(o) sdtia1(i) 22 0 lch 32 bick 18 0 l1 32 bick 18 0 r1 32 bick 18 0 l2 32 bick 18 0 r2 32 bick 18 0 l3 32 bick 18 0 r3 32 bick 32 bick 32 bick 22 0 rch 32 bick 22 23 19 19 19 19 19 23 19 23 19 lrcka lrcka (mode 8) (mode 12) figure 12. mode 8 ,12 timing 256 bick bicka(256fs) sdtoa(o) sdtia1(i) 22 0 lch 32 bick 22 0 l1 32 bick 22 0 r1 32 bick 22 0 l2 32 bick 22 0 r2 32 bick 22 0 l3 32 bick 22 0 r3 32 bick 32 bick 32 bick 22 0 rch 32 bick 22 23 23 23 23 23 23 23 23 23 23 lrcka lrcka (mode 9) (mode 13) figure 13. mode 9 ,13 timing 256 bick bicka(256fs) sdtoa(o) sdtia1(i) 22 0 lch 32 bick 22 0 l1 32 bick 22 0 r1 32 bick 22 0 l2 32 bick 22 0 r2 32 bick 22 0 l3 32 bick 22 0 r3 32 bick 32 bick 32 bick 22 0 rch 32 bick 22 22 23 23 23 23 23 23 23 23 23 23 lrcka lrcka (mode 10) (mode 14) figure 14. mode 10 ,14 timinig [ak4683] ms0427-e-02 2007/04 - 36 - 256 bick bicka(256fs) sdtoa(o) sdtia1(i) 23 0 lch 32 bick 23 0 l1 32 bick 23 0 r1 32 bick 23 0 l2 32 bick 23 0 r2 32 bick 23 0 l3 32 bick 23 0 r3 32 bick 32 bick 32 bick 23 0 rch 32 bick 23 23 lrcka lrcka (mode 11) (mode 15) figure 15. mode 11 ,15 timing 128 bick bicka(128fs) sdtoa(o) 22 0 lch 32 bick l1 32 bick r1 32 bick l2 32 bick r2 32 bick l3 32 bick r3 32 bick 32 bick 32 bick 22 0 rch 32 bick 22 23 23 23 sdtia1(i) 18 0 18 0 18 0 18 0 19 19 19 19 19 lrcka sdtia2(i) 18 0 18 0 19 19 19 lrcka (mode 16) (mode 20) figure 16. mode 16 ,20 timing 128 bick bicka(128fs) (mode 17) 22 0 lch 32 bick l1 32 bick r1 32 bick l2 32 bick r2 32 bick l3 32 bick r3 32 bick 32 bick 32 bick 22 0 rch 32 bick 22 23 23 23 sdtia1(i) 22 0 22 0 22 0 22 0 23 23 23 23 19 lrcka sdtia2(i) 22 0 22 0 23 23 19 lrcka (mode 21) figure 17. mode 17 ,21 timing [ak4683] ms0427-e-02 2007/04 - 37 - 128 bick bicka(128fs) sdtoa(o) 22 0 lch 32 bick l1 32 bick r1 32 bick l2 32 bick r2 32 bick l3 32 bick r3 32 bick 32 bick 32 bick 22 0 rch 32 bick 22 23 23 23 lrcka sdtia1(i) 22 0 22 0 22 0 22 0 23 23 23 23 22 23 sdtia2(i) 22 0 22 0 23 23 22 23 lrcka (mode 18) (mode 22) figure 18. mode 18 ,22 timing 128 bick bicka(128fs) sdtoa(o) 22 0 lch 32 bick l1 32 bick r1 32 bick l2 32 bick r2 32 bick l3 32 bick r3 32 bick 32 bick 32 bick 22 0 rch 32 bick 23 23 23 sdtia1(i) 22 0 22 0 22 0 22 0 23 23 23 23 23 sdtia2(i) 22 0 22 0 23 23 23 lrcka lrcka (mode 19) (mode 23) figure 19. mode 19 ,23 timing [ak4683] ms0427-e-02 2007/04 - 38 - digital volume control the ak4683 has channel-independent digital volume control (256 levels, 0.5db step). the attad7-0 bit set the volume level of each adc channel ( table 35), attda7-0 set each dac channel ( table 36). attad7-0 attenuation level 00h +24db 01h +23.5db 02h +22.0db : : 2fh +0.5db 30h 0db 31h -0.5db : feh -103db ffh mute (- ) (default) table 35.adc digital volume attda7-0 attenuation level 00h +12db 01h +11.5db 02h +11.0db : : 17h +0.5db 18h 0db 19h -0.5db : feh -115db ffh mute (- ) (default) table 36.dac digital volume transition time between set values of attad7-0 (attda7-0) bits can be selected by atsad (atsda) bits ( table 37, table 38). transition between set values of mode 0 and mode 1is the soft transition. th erefore, the switching noise does not occur in the transition. mode atsad att speed 0 0 1061/fs 1 1 256/fs (default) table 37. transition time between set values of attad7-0 bits (adc) mode atsda att speed 0 0 1061/fs 1 1 256/fs (default) table 38. transition time between set values of attda7-0 bits (dac) the transition between set values is soft transition of 1061 levels in mode 0. it takes 1061/fs (24ms@fs=48khz) from 00h to ffh(mute) in mode 0. if pdn pin goes to ?l?, th e attad7-0(attda7-0) bits are initialized to 30h(18h). the atts goes to their default value when rstn1 bit = ?0?. when rstn1 bit return to ?1?, the atts fade to their current value. [ak4683] ms0427-e-02 2007/04 - 39 - soft mute operation the adc and dac have the soft mute function. the soft mu te operation is performed at digital domain. when the smad/smda bits go to ?1?, the output signal is attenuated by - during att_data att transition time ( table 37, table 38) from the current att level. when the smad/smda bits are returned to ?0?, th e mute is cancelled and the output attenuation gradually changes to the att level during att_data att transition time. if the soft mute is cancelled before attenuating to - after starting the operation, the attenuation is discontinued and returned to att level by the same cycle. the soft mute is ef fective for changing the signal source w ithout stopping the signal transmission. smad/smda bits attenuation dzf (for smda) att level - aout 8192/fs gd gd (1) (2) (3) (4) (1) notes: (1) att_data att transition time ( table 37, table 38). for example, in norm al speed mode, this time is 1061/fs cycles (1792/fs) at att_ data=00h. att transition of the soft-mute is from 00h to ffh (2) the analog output corresponding to the digital input has a group delay, gd. (3) if the soft mute is cancelled before attenuating to - after starting the operation, the attenuation is discontinued and returned to att level by the same cycle. (4) when the input data at all the channels of the group are continuously zeros for 8192 cycles, dzf pin of each channel goes to ?h?. dzf pin immediately goes to ?l? if the input data of either channel of the group are not zero after going dzf ?h?. figure 20. soft mute and zero detection [ak4683] ms0427-e-02 2007/04 - 40 - input selector, input attenuator the ak4683 includes 6ch stereo input selectors ( figure 21). the input selector is 6 to 1 selector. the ain2-0 bits set the input channel ( table 39). ain2 bit ain1 bit ain0 bit input selector 0 0 0 lin1 / rin1 default 0 0 1 lin2 / rin2 0 1 0 lin3 / rin3 0 1 1 lin4 / rin4 1 0 0 lin5 / rin5 1 0 1 lin6 / rin6 1 1 0 none 1 1 1 none table 39. input selector the input atts are constructed by adding the input resistor (ri) for lin1-6/rin1-6 pins and the feedback resistor (rf) between lopin (ropin) pin and lisel (risel) pin ( figure 21). the voltage range of the lisel(risel) pin should be less than typ. 0.62 x avdd1 (vpp). if the input voltage of the input select or exceeds typ. 0.62 x avdd, the input voltage of the lisel(risel) pins must be attenuated to typ. 0.62 x avdd1 (vpp) by the input atts. the table 40 shows the example of ri and rf. lin1 lin2 lin3 lin4 lin5 rin1 rin2 rin3 rin4 rin5 ropin risel lopin lisel pre-amp pre-amp to adc to adc ri ri ri ri ri ri ri ri ri ri rf rf rin6 lin6 ri ri figure 21. input att input range ri [k ] rf [k ] att gain [db] lisel/r pin 4vrms 47 12 ? 11.86 1.02vrms (2.88vpp) 2vrms 47 24 ? 5.84 1.02vrms (2.88vpp) 1vrms 47 47 0 1vrms (2.82vpp) note: input range of internal adc is 0.62 x avdd1 (5v) = 3.1vpp typ. table 40. input att example [ak4683] ms0427-e-02 2007/04 - 41 - [input selector switching sequence] the input selector should be changed after soft mute to avoid the switching noise of the input selector ( figure 22). 1. enable the soft mute before changing channel. 2. change channel. 3. disable the soft mute. smute a ttenuation channel datt level - (1) (2) lin1/rin1 lin2/rin2 (1) figure 22. input channel sw itching sequence example the period of (1) varies in the setting value of datt. it takes 1028/fs to mute when datt value is +24db. when changing channels, the input channel should be changed during (2). the period of (2) should be around 200ms because there is some dc difference between the channels. [ak4683] ms0427-e-02 2007/04 - 42 - power on/off sequence the each block of the ak4683 are placed in the power-down mode by bringing pdn pin ?l? and both digital filters are reset at the same time. pdn pin ?l? also reset the control re gisters to their default values. in the power-down mode, the analog outputs go to vcom voltage and sdtoa,b, dzf/ovf pin go to ?l?. this reset should always be done after power-up. in slave mode, after exiting reset at power-up etc., the ak4683 starts to operate from the rising edge of lrck after mlck, then the device is in the power-down mode until mclk and lrck are input. in slave mode or internal loop mode, the ak4683 starts to operate by the input of mlck after exiting reset. the analog initialization cycle of ad c starts after exiting the power-down mode. therefore, the output data, sdto becomes available after 522/fs cycles of lrck clock. in case of the dac, an analog in itialization cycle starts after exiting the power-down mode. the analog outputs are vcom voltage during the initialization. figure 23 hows the sequences of the power-down and the power-up. the adc and all dacs can be powered-down individually by pwad bit , pwda bit and pwda2-1 bits. these bits don?t initialize the internal register values. when pwad b it = ?0? and selecting adc, the sdtoa(sdtob) pin goes to ?l?. when pwda bit and pwda1-2 bits = ?0?, the analog outputs go to vcom voltage and dzf/ovf pin go to ?h?. since some click noise may occur, th e analog output should muted externally if the click noise influences system application. a dc internal state pdn clock in mclk,lrck,sclk a dc in (analog) a dc out (digital) dac internal state dac in (digital) dac out (analog) external mute mute on (9) dzf1/dzf2 power power-down don?t care gd ?0?data power-down ?0?data gd (3) (3) (4) (6) (7) (8) 522/fs init cycle normal operation (1) gd normal operation gd (5) (6) 516/fs init cycle (2) 10 11/fs (10) mute on ?0?data ?0?data don?t care notes: (1) the analog part of adc is initiali zed after exiting the power-down state. (2) the analog part of dac is initiali zed after exiting the power-down state. (3) digital output corresponding to analog input and analog output corresponding to digital input have the group delay (gd). (4) adc output is ?0? data at the power-down state. (5) click noise occurs at the end of initialization of the an alog part. please mute the digital output externally if the click noise influences system application. (6) click noise occurs at the falling edge of pdn and at 512/fs(dac1) and 512/fs +96ms(dac2) after the rising edge of pdn. (7) when the external clocks (mclk, bicka (bickb), lrcka (lrckb)) are stopped, the ak4683 should be in the power-down mode. (8) dzf/ovf pin is ?l? in the power-down mode (pdn pin = ?l?). (9) please mute the analog output externally if th e click noise (6) influences system application. (10) dzf pin = ?l? for 10 11/fs after pdn= ? ?. figure 23. power-down/up sequence example [ak4683] ms0427-e-02 2007/04 - 43 - status of analog output pins during power-down (pdn pin =?l?) the status of analog output pins is as follows. pin name hpl/hpr hvss lout1/rout1/lout2/rout2 vcom lisel/risel hi-z reset function when rstn1 bit = ?0?, adc and dacs are powered-down but the internal re gister are not initialized. the analog outputs go to vcom voltage, dzf/ovf pin goes to ?h? and sdtoa/b pins go to ?l?. because some click noise occurs, the analog output should be muted externally if the click noise influences system application. the figure 24 shows the power-up sequence. a dc internal state rstn bit normal operation digital block power-down normal operation don?t care gd gd clock in mclk,lrck,sclk a dc in (analog) ?0?data a dc out (digital) normal operation normal operation dac internal state ?0?data dac in (digital) dac out (analog) gd gd (2) (2) (3) (4) (6) (6) dzf1/dzf2 (7) internal rstn bit digital block power-down 1~2/fs (9) 4~5/fs (9) 4 5/fs (8) (5) 516/fs init cycle (1) notes: (1) the analog part of adc is initialized after exiting the reset state. (2) digital output corresponding to analog input and analog output corresponding to digital input have the group delay (gd). (3) adc output is ?0? data at the power-down state. (4) click noise occurs when the internal rstn bit becomes ?1 ?. please mute the digital output externally if the click noise influences system application. (5) when rstn1 bit = ?0?, the analog outputs go to vcom voltage. (6) click noise occurs at 4 5/fs after rstn1 bit becomes ?0?, and occurs at 1 2/fs after rstn1 bit becomes ?1?. this noise is output even if ?0? data is input. (7) the external clocks (mclk, bicka (bickb), lrck a (lrckb)) can be stopped in the reset mode. when exiting the reset mode, ?1? should be written to rstn1 b it after the external clocks (mclk, bicka (bickb), lrcka (lrckb)) are fed. (8) dzf pins go to ?h? when the rstn 1 bit becomes ?0?, and go to ?l? at 6~7/fs after rstn1 bit becomes ?1?. (9) there is a delay, 4~5/fs from rstn1 bit ?0? to the internal rstn bit ?0?. figure 24. reset sequence example [ak4683] ms0427-e-02 2007/04 - 44 - headphone output power supply voltage for the headphone-amp is supplied from the hvdd pin and centered on the hvdd/2 voltage. when the muten bit is ?0?, the common voltage of headphone-amp falls and the outputs (hpl and hpr pins) go to ?l? (hvss). when the muten bit is ?1 ?, the common voltage rises to hvdd/2 . a capacitor between the mutet pin and ground reduces click noise at power-up. rise/fall time constant is proportional to hv dd voltage and the capacitor at mutet pin. [example]: a capacitor between the mutet pin and ground = 1.0 f, hvdd=5v: rise/fall time constant: = 120ms(typ) when pwhp bit is ?0?, the headphon e-amp is powered-down, and the outputs (hpl and hpr pins) go to ?l? (hvss). pwhp bit (1) (2) ( ) ( ) muten bit hpl pin, hpr pin (3) figure 25. power-up/power-down timing for headphone-amp (1) headphone-amp power-up (pwhp bit = ?1?). the outputs are still hvss. (2) headphone-amp common voltage rises up (muten bit = ?1?). common voltage of headphone-amp is rising. (3) start the audio output after finishing the setup pf common voltage to prevent the clipping. (4) headphone-amp common voltage falls down (muten bit = ?0?). common voltage of headphone-amp is falling. (5) headphone-amp power-down (pwhp bit = ?0?). the outputs are hvss. if the power supply is switched off or headphone-amp is powered-down before the common voltage goes to hvss, some click noise occurs. the cut-off frequency (fc) of headphone-amp depends on the external resistor and capacitor. table 41 shows the cut off frequency and the output power for various resistor/capacitor combinations. the headphone impedance r l is 16 . output powers are shown at hvdd = 5v. ak4683 hp-amp 16 headphone r c figure 26. external circuit example of headphone r [ ] c [ f] fc [hz] output power [mw]@0dbfs 220 45 0 100 100 50 100 70 6.8 47 149 25 100 50 16 47 106 12.5 table 41. external circuit example [ak4683] ms0427-e-02 2007/04 - 45 - output analog volume (opga) volume range of the output analog volume is 0db to -50db and mute with by zero crossing detection. the opga is operated by the clock for dac. the zero crossing detection of lch and rch is worked independently. if there are no zero-crossings, the level will then change after a timeout period ; the timeout period scales with fs. when zce is ?0?, it is changed immediately without zero crossing detection. when writing to opga4-0 bits continually, it should take an interval of zero crossing timeout period or more. if the opga4-0 bits are changed before zero crossing, the volume of lch and rch may differ. when the volume that is same as the present is set, the zero crossing counter isn?t reset and timeout according to the previous writing timing. opga4-0 gain(db) step level 1fh +0 1eh -1 1dh -2 : : 10h -15 0fh -16 1db 17 0eh -18 0dh -20 : : 05h -36 04h -38 2db 11 03h -42 02h -46 01h -50 4db 3 00h mute 1 (default) table 42. output analog volume setting when zce bit is ?1?, the lch/rch volume level are changed independently by zero crossing detection or zero crossing timeout operation. the count of timer is doubled when dac double speed mode, four times when dac quad speed mode. dac2 sampling speed zero crossing timeout normal speed mode 768/fs (16ms @fs=48khz) double speed mode 1536/fs (16ms @fs=96khz) quad speed mode 3072/fs (16ms @fs=192khz) table 43. zero crossing timeout the opga is enable at pwda bit = pwda2 bit = ?1?. the initializing of opga starts when dac is powered up. this initializing cycle is 96ms(@fs=48khz). wr iting to the opga4-0 during the initialization is ignored. the default volume value is mute after power up. initialization time is 512/fs+96ms(@fs=48khz) after pdn pin = ?h?. dac2 sampling speed opga initialization time normal speed mode 4608/fs (96ms @fs=48khz) double speed mode 9216/fs (96ms @fs=96khz) quad speed mode 18432/fs (96ms @fs=192khz) table 44. opga initialization time [ak4683] ms0427-e-02 2007/04 - 46 - operation overview (dir/dit part) 192khz clock recovery on chip low jitter pll has a wide lock range with 32khz to 192khz and the lock time is less than 20ms. the ak4683 has the sampling frequency detect function. by either the cl ock comparison against x?tal oscillator or using the channel status, the ak4683 detects the sampling frequency (32khz, 44.1khz, 48khz, 88.2khz, 96khz, 176.4khz and 192khz). the pll loses lock when the recei ved sync interval is incorrect. clock operation mode when dir is selected. the cm0/cm1 bits select the clock source and the data source of sdto. in mode 2, the clock source is automatically switched from pll to xti/mclk2 when pll goes unlock state. in mode 3, the clock source is fixed to xti/mclk2, but pll is also operating and the recovered data such as c bits can be monitored. for mode 2 and 3, it is recommended that the frequency of xti/mclk2 is different from the recovered frequency from pll. mode cm1 cm0 unlock pll clock source sdto 0 0 0 - on pll rx 1 0 1 - off extclk dit source 0 on pll rx 2 1 0 1 on extclk dit source 3 1 1 - on extclk dit source (default) on: oscillation (power-up), off: stop (power-down) table 45. clock operation mode select when 384fs of xti/mclk2 is supplied to dir/dit, cksdt bit should be set to ?1?. cksdt bit clock speed 0 x 1 (default) 1 x 2/3 table 46. xti/mclk2 speed [ak4683] ms0427-e-02 2007/04 - 47 - sampling frequency and pre-emphasis detection the ak4683 has two methods for detecting the sampling frequency as follows. 1. clock comparison between recovered clock and xti/mclk2 2. sampling frequency information on channel status those could be selected by xtl1, 0 bits. and the detected frequency is reported on fs3-0 bits. xtl1 xtl0 xti/mclk2 frequency 0 0 11.2896mhz 0 1 12.288mhz 1 0 24.576mhz 1 1 (use channel status) (default) table 47. reference xti/mclk2 frequency except xtl1,0= ?1,1? xtl1,0= ?1,1? register output fs consumer mode (note 2) professional mode fs3 fs2 fs1 fs0 clock comparison (note 1) byte3 bit3,2,1,0 byte0 bit7,6 byte4 bit6,5,4,3 0 0 0 0 44.1khz 44.1khz 0 0 0 0 0 1 0 0 0 0 0 0 0 1 reserved reserved 0 0 0 1 (others) 0 0 1 0 48khz 48khz 0 0 1 0 1 0 0 0 0 0 0 0 1 1 32khz 32khz 0 0 1 1 1 1 0 0 0 0 1 0 0 0 88.2khz 88.2khz ( 1 0 0 0 ) 0 0 1 0 1 0 1 0 1 0 96khz 96khz ( 1 0 1 0 ) 0 0 0 0 1 0 1 1 0 0 176.4khz 176.4khz ( 1 1 0 0 ) 0 0 1 0 1 1 1 1 1 0 192khz 192khz ( 1 1 1 0 ) 0 0 0 0 1 1 note1: at least 3% range is identified as the value in the table 48. in case of intermediate frequency of those two, fs3-0 bits indicate nearer value. when the frequency is much bigger than 192khz or much smaller than 32khz, fs3-0 bits may indicate ?0001?. note2: when consumer mode, byte3 bit3-0 are copied to fs3-0 bits. table 48. fs information the pre-emphasis information is detected and reported on pem bit. this information is extracted from channel 1 at default. it can be switched to channel 2 by cs12 bit in control register. pem pre-emphasis byte 0 bits 3-5 0 off 0x100 1 on 0x100 table 49. pem in consumer mode pem pre-emphasis byte 0 bits 2-4 0 off 110 1 on 110 table 50. pem in professional mode [ak4683] ms0427-e-02 2007/04 - 48 - de-emphasis filter control the ak4683 includes the digital de-emphasis filter (tc=50/15s) by iir filter corresponding to four sampling frequencies (32khz, 44.1khz, 48khz and 96k hz). when deau bit=?1?, the de-emphasis filter is enabled automatically by sampling frequency and pre-emphasis information in the channel status. the ak4683 goes this mode at default. therefore, in parallel mode, the ak4683 is always placed in this mode and the status bits in channel 1 control the de-emphasis filter. in serial mode, dem0/1 and dfs bits can control the de-emphasis filter when deau bit is ?0?. the internal de-emphasis filter is bypassed and the recovered data is output without any change if either pre-emphasis or de-emphasis mode is off. pem fs3 fs2 fs1 fs0 mode 1 0 0 0 0 44.1khz 1 0 0 1 0 48khz 1 0 0 1 1 32khz 1 1 0 1 0 96khz 1 (others) off 0 x x x x off table 51. de-emphasis auto control at deau bit = ?1? (default) pem dfs dem1 dem0 mode 1 0 0 0 44.1khz 1 0 0 1 off (default) 1 0 1 0 48khz 1 0 1 1 32khz 1 1 0 0 off 1 1 0 1 off 1 1 1 0 96khz 1 1 1 1 off 0 x x x off table 52. de-emphasis manual control at deau bit = ?0? system reset and power-down the ak4683 has a power-down mode for all circuits by pdn pin can be partially powerd-down by pwn bit. the rstn2 bit initializes the register and resets the internal tim ing. the ak4683 should be reset once by bringing pdn pin = ?l? upon power-up. pdn pin: all analog and digital circu it are placed in the power-down and reset mode by bringing pdn pin = ?l?. all the registers are initialized, and clocks are stoppe d. reading/witting to the register are disabled. rstn2 bit: all the registers except pwn and rstn2 bits are initialized by bringing rstn2 bit = ?0?. the internal timings are also initialized. when rstn2 bit = ?0?, th e clock are output but sdto pin is hold to ?l?. witting to the register is not available except pwn an d rstn2 bits. reading to the register is disabled. pwn bit: the clock recovery part is initialized by bringing pw n bit = ?0?. in this case, clocks from pll are stopped. the registers are not initialized and the mode settings are kept. writing and reading to the registers are enabled. [ak4683] ms0427-e-02 2007/04 - 49 - biphase input and through output eight receiver inputs (rx0-3) are available in serial control mode. only the rx0 input includes amplifier corresponding to unbalance mode and can accept the signal of 200mv or more. ips1 -0 bits select the receiver channel. the v bit can be output via pin. ips1 bit ips0 bit dir source 0 0 rx0 (default) 0 1 rx1 1 0 rx2 1 1 rx3 table 53. recovery data select (b) vout lrck (except i 2 s) v(l0) v(r0) v(l1) v(r39) v(l39) v(l40) c(r191) 1/4fs sdto l191 r191 l38 l39 r38 l0 r190 lrck (i 2 s) figure 27. v output timings [ak4683] ms0427-e-02 2007/04 - 50 - biphase output the ak4683 can output either the through output (from rx) or transmitter output (dit) via tx pin. those could be selected by dit bit. the source of the through output from tx0 could be selected among rx0-3 by ops0, 1 bits. when output dit data, v bit could be controlled by vin bit and first 5 bytes of c bit could be controlled by ct39-ct0 bits in control registers. when bit0= ?0?(consumer mode), bit20-23 (audio channel) could not be controlled directly but be controlled by ct20 bit. when the ct20 bit is ?1?, the ak4683 outputs ?1000? as c20-23 for left channel and outputs ?0100? at c20-23 for right channel automatically. when ct20 bit is ?0?, the ak4683 outputs ?0000? set as ?1000? for sub frame 1, and ?0100? for sub fr ame 2. u bits are fixed to ?0?. dit bit ops1 bit ops0 bit tx source 0 0 0 rx0 (default) 0 0 1 rx1 0 1 0 rx2 0 1 1 rx3 1 * * dit table 54. tx source control cm1-0 bit, clkdt bit, cksdt bit and ocks1-0 select the clock source of dit. this clock must be the same clock as the clock sources of port connecting to dit. cm1 cm0 unlock clock source 0 0 - rmck 0 1 - extclk 0 rmck 1 0 1 extclk 1 1 - extclk (default) table 55. clock mode control clkdt bit clock source 0 xti 1 mclk2 table 56. extclk control cksdt ocks1 ocks0 extclk fs(max) 0 0 0 256fs 96khz 0 0 1 256fs 96khz 0 1 0 512fs 48khz 0 1 1 128fs 192khz 1 0 0 384fs 48khz 1 0 1 384fs 48khz 1 1 0 768fs 32khz 1 1 1 192fs 96khz table 57. mclko speed [ak4683] ms0427-e-02 2007/04 - 51 - the ditd1-0 bits control the data source of dit. ditd1 bit ditd0 bit dit source 0 0 dir 0 1 adc 1 0 sdtib 1 1 sdtia1(default) table 58. dit source control biphase signal input/output circuit (rx0, tx) rx0 ak4683 0.1uf 75 coax 75 figure 28. consumer input circuit (coaxial input) note: in case of coaxial input, if a coupling le vel to this input from the next rx input line pattern exceeds 50mv, there is a possibility to occu r an incorrect operation. in this case, it is possible to lower the coupling level by adding this decoupling capacitor. rx0-3 ak4683 470 o/e optical receiver optical fiber figure 29. consumer input circuit (optical input) in case of coaxial input, as the input level of rx0 line is small, be careful not to crosstalk among rx input lines. for example, by inserting the shield pattern among them. the ak4683 includes the tx output buffer. the output level meets combination 0.5v+/-20% using the external resistor network. the t1 in figure 30 is a transformer of 1:1. tx dvss 100 2% t1 75 cable 330 2% figure 30. tx external resistor network [ak4683] ms0427-e-02 2007/04 - 52 - q-subcode buffers the ak4683 has q-subcode buffer for cd application. the ak4683 takes q-subcode into registers by following conditions. 1. the sync word (s0,s1) is c onstructed at least 16 ?0?s. 2. the start bit is ?1?. 3. those 7bits q-w follows to the start bit. 4. the distance between two st art bits are 8-16 bits. the qint bit in the control register go es ?1? when the new q-subcode differs from old one, and goes ?0? when qint bit is read. 1 2 3 4 5 6 7 8 * s0 0 0 0 0 0 0 0 0 0? s1 0 0 0 0 0 0 0 0 0? s2 1 q2 r2 s2 t2 u2 v2 w2 0? s3 1 q3 r3 s3 t3 u3 v3 w3 0? : : : : : : : : : : s97 1 q97 r97 s97 t97 u97 v97 w97 0? s0 0 0 0 0 0 0 0 0 0? s1 0 0 0 0 0 0 0 0 0? s2 1 q2 r2 s2 t2 u2 v2 w2 0? s3 1 q3 r3 s3 t3 u3 v3 w3 0? : : : : : : : : : : (*) number of "0" : min=0; max=8. figure 31. configuration of u-bit(cd) q2 q3 q4 q5 q6 q7 q8 q9 q10 q11 q12 q13 q14 q15 q16 q17 q18 q19 q20 q21 q22 q23 q24 q25 ctrl adrs track number index q26 q27 q28 q29 q30 q31 q32 q33 q34 q35 q36 q37 q38 q39 q40 q41 q42 q43 q44 q45 q46 q47 q48 q49 minute second frame q50 q51 q52 q53 q54 q55 q56 q57 q58 q59 q60 q61 q62 q63 q64 q65 q66 q67 q68 q69 q70 q71 q72 q73 zero absolute minute absolute second q74 q75 q76 q77 q78 q79 q80 q81 q82 q83 q84 q85 q86 q87 q88 q89 q90 q91 q92 q93 q94 q95 q96 q97 absolute frame crc g(x)=x 16 +x 12 +x 5 +1 figure 32. q-subcode addr register name d7 d6 d5 d4 d3 d2 d1 d0 16h q-subcode address / control q9 q8 q3 q2 17h q-subcode track q17 q16 q11 q10 18h q-subcode index 19h q-subcode minute 1ah q-subcode second 1bh q-subcode frame 1ch q-subcode zero 1dh q-subcode abs minute 1eh q-subcode abs second 1fh q-subcode abs frame q81 q80 q75 q74 figure 33. q-subcode register q [ak4683] ms0427-e-02 2007/04 - 53 - error handling there are the following eight events that make int pin ?h?. int pin show the status of following conditions. 1. unlock: ?1? when the pll loses lock. the ak4683 loses lock when the distance between two preambles is not correct or when those preambles are not correct. 2. par: ?1? when parity error or biphase coding error is detected, and keeps ?1? until this register is read. updated every sub-frame cycle. read ing this register resets itself. 3. auto: ?1? when non-pcm bitstream is detected. updated every 4096 frames cycle. 4. dtscd: ?1? when dts-cd bitstream is detected. updated every dts-cd sync cycle. 5. audion: ?1? when the ?audio? bit in re covered channel status indicates ?1?. updated every block cycle. 6. pem: ?1? when ?pem? in recovere d channel status indicates ?1?. updated every block cycle. 7. qint: ?1? when q-subcode differ from old one, and keeps ?1? until this register is read. updated every sync code cycle for q-subcod e. reading this register resets itself. 8. cint: ?1? when received c bits differ from old one, and keeps ?1? until this register is read. updated every block cycle. readin g this register resets itself. int pin is fixed to ?l? when the pll is off (cm1,0= ?01?). once the int pin goes to ?h?, this pin holds ?h? for 1024/fs cycles (this value can be changed by efh0/1 bits) after those events are removed. int pin can mask those eight events individually. once par, qint and cint bit goes to ?1 ?, those registers are held to ?1? until those registers are read. while the ak4683 loses lock, registers regarding c-bit or u-bits are not initialized and keep previous value. int pin outputs the ored signal among those eight events. however, each mask bits can mask each event. when each bit masks those events, the event does not affect int pin operation (those mask do not affect those registers (unlock, par, etc.) themselves. once int pin go es ?h?, it maintains ?h? for 1024/fs cycles (this value can be changed by efh0-1 bits) after the all events are removed. once those pa r, qint or cint bit goes ?1?, it holds ?1? until reading those registers. while the ak4683 loses lock, the channel status q-subcode bits are not updated and hold the previous data. at initial state, int outputs the ored signal between unlock and par. event pin unlock par auto dtscd audion pem qint cint sdto* v* tx* 1 x x x x x x x ?l? ?l? output 0 1 x x x x x x previous data output output 0 0 1 x x x x x output output output 0 0 x 1 x x x x output output output 0 0 x x 1 x x x output output output 0 0 x x x 1 x x output output output 0 0 x x x x 1 x output output output 0 0 x x x x x 1 output output output note: when selected. table 59. error handling [ak4683] ms0427-e-02 2007/04 - 54 - error (unlock, par,..) sdto (unlock) note mcko, bick, lrck (unlock) note previous data register (par,cint,qint) hold ?1? command read 06h mcko, bick, lrck (except unlock) note (fs: around 20khz) sdto (par error) note reset (error) sdto (others) note normal operation int pin hold time (max: 4096/fs) register (others) free run vpin (unlock) note vpin (except unlock) note note: when dir is selected as source. figure 34. int0/1 pin timing [ak4683] ms0427-e-02 2007/04 - 55 - int pin ="h" no ye s ye s initialize pdn pin ="l" to "h" read 06h mute dac output read 06h no (each error handling) read 06h (resets registers) int pin ="h" release muting figure 35. error handling sequence example 1 [ak4683] ms0427-e-02 2007/04 - 56 - int pin ="h" no ye s initialize pdn pin ="l" to "h" read 06h read 06h and detect qsub= ?1? no (read q-buffer) new data is valid int pin ="l" qcrc = ?0? yes yes new data is invalid no figure 36. error handling sequence example 2 (for q/cint) [ak4683] ms0427-e-02 2007/04 - 57 - non-pcm (ac-3, mpeg, etc.) and dts-cd bitstream detection the ak4683 has a non-pcm steam auto-detection function. when the 32bit mode non-pcm preamble based on dolby ?ac-3 data stream in iec60958 interface? is detected, the auto b it goes ?1?. the 96bit sync code consists of 0x0000, 0x0000, 0x0000, 0x0000, 0xf872 and 0x4e1f. detection of this pattern will set the auto bit ?1?. once the auto bit is set ?1?, it will remain ?1? until 4096 frames pass through the chip without additional sync pattern being detected. when those preambles are detected, the bur st preambles pc and pd that follow thos e sync codes are stored to registers. the ak4683 also has the dts-cd bitstream auto-detection function. when the ak4683 detects dts-cd bitstreams, dtscd bit goes to ?1?. when the next sync code does not come within 4096 flames, dtscd bit goes to ?0? until when the ak4683 detect s the stream again. burst preambles in non-pcm bitstreams 0 16 bits of bitstream 3 4 7 8 11 12 27 28 29 30 31 preamble aux. lsb msb v u c p sub-frame of iec60958 015 pa pb pc pd burst_payload stuffing repetition time of the burst figure 37. data structure in iec60958 preamble word length of field contents value pa 16 bits sync word 1 0xf872 pb 16 bits sync word 2 0x4e1f pc 16 bits burst info see table 61 pd 16 bits length code numbers of bits table 60. burst preamble words [ak4683] ms0427-e-02 2007/04 - 58 - bits of pc value contents repetition time of burst in iec60958 frames 0-4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16-31 data type null data dolby ac-3 data reserved pause mpeg-1 layer1 data mpeg-1 layer2 or 3 data or mpeg-2 without extension mpeg-2 data with extension mpeg-2 aac adts mpeg-2, layer1 low sample rate mpeg-2, layer2 or 3 low sample rate reserved dts type i dts type ii dts type iii atrac atrac2/3 reserved 4096 1536 384 1152 1152 1024 384 1152 512 1024 2048 512 1024 5, 6 0 reserved, shall be set to ?0? 7 0 1 error-flag indicating a valid burst_payload error-flag indicating that the burst_payload may contain errors 8-12 data type dependent info 13-15 0 bit stream number, shall be set to ?0? (refer the iec standards.) table 61. fields of burst info pc [ak4683] ms0427-e-02 2007/04 - 59 - non-pcm bitstream timing 1) when non-pcm preamble is not coming within 4096 frames, pa pc 1 pd 1 pb pa pc 2 pd 2 pb pa pc 3 pd 3 pb ?0? pc 1 pc 2 ?0? pd 1 pd 2 pd 3 pc 3 pdn pin bit stream a uto bit pc register pd registe r repetition time >4096 frames figure 38. timing example 1 2) when non-pcm bitstream stops (when mulk0=0), pa pc 1 pd 1 pb stop pa pc n pd n pb pc 0 pc 1 pd 0 pd 1 pd n pc n int0 pin bit stream a uto bit pc register pd registe r int0 hold time 2~3 syncs (b,m or w) <20ms (lock time) [ak4683] ms0427-e-02 2007/04 - 61 - (2). i 2 c bus control mode (i2c pin = ?h?) ak4683 supports the standard-mode i 2 c-bus (max: 100khz). then ak4683 does not support a fast-mode i 2 c-bus system (max: 400khz). (2)-1. data transfer all commands are preceded by a start condition. after th e start condition, a slave address is sent. after the ak4683 recognizes the start c ondition, the device interfaced to the bus waits for the slave address to be transmitted over the sda line. if the transmitted slave address matches an address for one of the devices, the designated slave device pulls the sda line to low (acknowledge). the data transfer is always terminated by a stop condition generated by the master device. (2)-1-1. data validity the data on the sda line must be stable during the high period of the clock. the high or low state of the data line can only change when the clock signal on the scl line is low except for the start and the stop condition. scl sda data line stable : data valid change of data a llowed figure 41. data transfer (2)-1-2. start and stop condition a high to low transition on the sda line while scl is hi gh indicates a start condition. all sequences start from the start condition. a low to high transition on the sda line while scl is high defines a stop condition. all sequences end by the stop condition. scl sda stop condition start condition figure 42. start and stop conditions [ak4683] ms0427-e-02 2007/04 - 62 - (2)-1-3. acknowledge acknowledge is a software convention used to indicate successful data transfers. the transmitting device will release the sda line (high) after transmitting eight b its. the receiver must pull dow n the sda line during the acknowledge clock pulse so that that it remains stable ?l? during ?h? period of this clock pulse. the ak4683 will generates an acknowledge after each byte has been received. in the read mode, the slave, the ak4683 will transmit eight b its of data, release the sda line and monitor the line for an acknowledge. if an acknowledge is detected and no stop condition is generated by the master, the slave will continue to transmit data. if an acknowledge is not detected, the sl ave will terminate further data transmissions and await the stop condition. the register of adc/dac part can not ge nerate acknowledge fo r read operations. scl from master acknowledge data output by transmitter data output by receiver 1 9 8 start condition clock pulse for acknowledge not acknowledge figure 43. acknowledge on the i 2 c-bus (2)-1-4. first byte the first byte, which includes seven bits of slave address an d one bit of r/w bit, is sent after the start condition. if the transmitted slave address matches an address for one of the device, the recei ver who has been addressed pulls down the sda line. the most significant five bits of the sl ave address are fixed as ?00100?. the next two bits are cad1 and cad0 (device address bits). these two bits identify th e specific device on the bus. the eighth bit (lsb) of the first byte (r/w bit) defines whether a write or read condition is requested by the master. a ?1? indicates that the read operation is to be executed. a ?0? indicates that the write operation is to be executed. 0 0 1 0 0 cad1 cad0 r/w (cad1-cad0 = fixed to ?10? for adc/dac part, ?00? for dir/dit part) figure 44. the first byte [ak4683] ms0427-e-02 2007/04 - 63 - (2)-2. write operations set r/w bit = ?0? for the write operation of the ak4683. after receipt the start condition and the first byte, the ak4683 generates an ack nowledge, and awaits the second byte (register address). the second byte consists of the address for control registers of ak4683. the format is msb first, and those most significant 3-bits are ?don?t care?. * * * a4 a3 a2 a1 a0 (*: don?t care) figure 45. the second byte after receipt the second byte, the ak4683 generates an acknow ledge, and awaits the third byte. those data after the second byte contain control data. the format is msb first, 8bits. d7 d6 d5 d4 d3 d2 d1 d0 figure 46. byte structure after the second byte the ak4683 is capable of more than one byte write operation by one sequence. after receipt of the third byte, the ak4683 generates an ack nowledge, and awaits the next data again. the master can transmit more than one words instead of terminating the write cycle after the first data word is transferred. after the receipt of each data, the internal 5bits address counter is incremented by one, and the next data is taken into next address automatically. if the address exceed 1fh prior to ge nerating the stop condition, the address counter will ?roll over? to 00h and the previous data will be overwritten. sda s t a r t a c k a c k s slave a ddress a c k registe r a ddress(n) data(n) p s t o p data(n+x) a c k data(n+1) figure 47. write operation [ak4683] ms0427-e-02 2007/04 - 64 - (2)-3. read operations set r/w bit = ?1? for the read operation of the ak4683. after transmission of a data, the master can read next address?s data by generating the acknowledge instead of terminating the write cycle after the receipt the first data word. after the receipt of each data, the internal 5bits address counter is incremented by one, and the next data is take n into next address automatically. if the address exceed 1fh prior to generating the stop condition, the address counter will ?roll over? to 00h and the previous data will be overwritten. the ak4683 supports two basic read operations: current address read and random read. adc/dac part register can not read. (2)-3-1. current address read the ak4683 contains an internal address counter that maintains the address of the last word accessed, incremented by one. therefore, if the last access (either a read or write ) was to address n, the next current read operation would access data from the address n+1. after receipt of the slave addr ess with r/w bit set to ?1?, the ak4683 gene rates an acknowledge, transmits 1byte data which address is set by the internal address counter and increm ents the internal address counte r by 1. if the master does not generate an acknowledge to the data but generate the stop condition, the ak4683 discontinues transmission sda s t a r t a c k a c k s slave a ddress a c k data(n) data(n+1) p s t o p data(n+x) a c k data(n+2) figure 48. current address read (2)-3-2. random read random read operation allows the master to access any memory location at random. prior to issuing the slave address with the r/w bit set to ?1?, the master must first perform a ?dummy? write operation. the master issues the start condition, sl ave address(r/w=?0?) and then the regist er address to read. after the register address?s acknowledge, the master immediately reissues the st art condition and the slave address with the r/w bit set to ?1?. then the ak4683 generates an ackno wledge, 1byte data and increments the internal address counter by 1. if the master does not generate an acknowledge to the data but generate the stop condition, the ak4683 discontinues transmission. sda s t a r t a c k a c k ss s t a r t slave a ddress word a ddress(n) slave a ddress a c k data(n) a c k p s t o p data(n+x) a c k data(n+1) figure 49. random read [ak4683] ms0427-e-02 2007/04 - 65 - register map (adc/dac part) addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h powerdown 1 pwxtl muten pwvr pwhp 0 smad smda rstn1 01h powerdown 2 pwpob pwpo a pwda pwad 0 0 pwda2 pwda1 02h clock select 1 0 0 0 0 clkb1 clkb0 clka1 clka0 03h clock select 2 cksl2 cksl1 c ksl0 clkl1 clkl0 mcko1 mcko0 clkdt 04h clock select 3 cksai2 cksai1 cksai0 0 olra1 olra0 bcaf msa 05h clock select 4 0 xtl1 x tl0 cksdt cksb2 cksb1 cksb0 msb 06h sampling speed 0 acksai acksao acksb 0 dfsad dfsda1 dfsda0 07h data source select 1 0 0 ditd1 ditd0 sdtob1 sdtob0 sdtoa1 sdtoa0 08h data source select 2 0 dac22 dac21 dac20 0 dac12 dac11 dac10 09h analog input control 0 0 0 0 0 ain2 ain1 ain0 0ah audio data format 0 0 difb1 difb0 tdma1 tdma0 difa1 difa0 0bh de-emphasis/ att speed dem11 dem10 dem21 dem20 0 atsad 0 atsda 0ch lin volume control attad7 attad6 attad5 attad4 attad3 attad2 attad1 attad0 0dh rin volume control attad7 attad6 attad5 attad4 attad3 attad2 attad1 attad0 0eh lout1 volume control attda7 attda6 attda5 attda4 attda3 attda2 attda1 attda0 0fh rout1 volume control attda7 attda6 attda5 attda4 attda3 attda2 attda1 attda0 10h lout2 volume control attda7 attda6 attda5 attda4 attda3 attda2 attda1 attda0 11h rout2 volume control attda7 attda6 attda5 attda4 attda3 attda2 attda1 attda0 12h hpl volume control 0 0 0 opga4 opga3 opga2 opga1 opga0 13h ovf/dzf/v control 0 0 zce vin func1 func0 dzfm1 dzfm0 note: for addresses from14h to 1fh, data must not be written. when pdn pin goes to ?l?, the registers are initialized to their default values. when rstn1 bit goes to ?0?, the internal timing is reset and dzf pin goes to ?h?, but registers are not initialized to their default values. [ak4683] ms0427-e-02 2007/04 - 66 - register definitions addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h powerdown 1 pwxtl muten pwvr pwhp 0 smad smda rstn1 default 1 0 1 0 0 0 0 1 rstn1: internal timing reset 0: reset. dzf pin go to ?h?, but registers are not initialized. 1: normal operation (default) smda: dac soft mute enable 0: normal operation (default) 1: all dac outputs soft-muted smad: adc soft mute enable 0: normal operation (default) 1: adc outputs soft-muted pwhp: power management for headphone amplifier 0: power off (default) 1: power on pwvr: power management for reference voltage 0: power off 1: power on (default) muten: bias voltage control for headphone amp 0: bias = 0v (default). 1: normal operation. bias = 0.5xhvdd(typ). pwxtl: power management for x?tal oscillator 0: power off 1: power on (default) [ak4683] ms0427-e-02 2007/04 - 67 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 01h powerdown 2 pwpob pwpo a pwda pwad 0 0 pwda2 pwda1 default 1 1 1 1 0 0 1 1 pwda1: power-down control of dac1 analog 0: power-down 1: normal operation (default) pwda2: power-down control of dac2 analog 0: power-down 1: normal operation (default) pwad: power-down control of adc 0: power-down 1: normal operation (default) pwda: full-power-down control of dac1-2 0: power-down 1: normal operation (default) pwpoa: power-down control of porta 0: power-down 1: normal operation (default) pwpob: power-down control of portb 0: power-down 1: normal operation (default) addr register name d7 d6 d5 d4 d3 d2 d1 d0 02h clock select 1 0 0 0 0 clkb1 clkb0 clka1 clka0 default 0 0 0 0 0 1 0 1 clka1-0: clock source control for porta 00: dir 01: x?tal(xti) (default) 10: mclk2 11: (reserved) clkb1-0: clock source control for portb 00: dir 01: x?tal(xti) (default) 10: mclk2 11: (reserved) [ak4683] ms0427-e-02 2007/04 - 68 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 03h clock select 2 cksl2 cksl1 cksl0 clkl1 clkl0 mcko1 mcko0 clkdt default 0 1 0 0 1 0 1 0 clkdt: clock source control for dit refer table 56. mclko1-0: clock source control for mclko refer table 4. clkl1-0: clock source control for clock gen c 00: dir 01: x?tal(xti) (default) 10: mclk2 11: (reserved) clsl2-0: clock control for clock gen c refer table 15 addr register name d7 d6 d5 d4 d3 d2 d1 d0 04h clock select 3 cksai2 cksai1 cksai0 selao olra1 olra0 bcaf msa default 0 1 0 0 0 0 0 0 msa: master/slave control for input data of porta. refer table 16. bcaf: bit clock control for porta refer table 13. olra1-0: clock control for porta olrcka. refer table 12. selao: clock control for dir/dit 0: except for the case at ?1?. (default) 1: selects when the frequency of ilrcka and olrcka are different, ditd[1:0]= ?00? or ?01? and both sdtoa[1:0] and ditd[1 :0] select same data source. cksai2-0: clock control for porta input data. refer table 11. [ak4683] ms0427-e-02 2007/04 - 69 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 05h clock select 4 0 xtl1 xtl0 cksdt cksb2 cksb1 cksb0 msb default 0 0 0 0 0 1 0 0 msb: master/slave control for input data of portb. refer table 17. cksb2-0: clock control for portb. refer table 14. cksdt: clock control for dit. refer table 57. xtl1-0: x?tal frequency control 00: 11.2896mhz (default) 01: 12.288mhz 10: 24.576mhz 11: (channel status) addr register name d7 d6 d5 d4 d3 d2 d1 d0 06h sampling speed 0 acksai acksao acksb 0 dfsad dfsda1 dfsda0 default 0 0 0 0 0 0 0 0 dfsda1-0: dac sampling speed control these settings are ignored in auto setting mode. refer table 22. dfsad: adc sampling speed control this setting is ignored in auto setting mode. refer table 21. acskb: auto setting mode of portb 0: disable, manual setting mode (default) 1: enable, auto setting mode master clock frequency is detected automatically at acksb bit ?1?. in this case, the setting of dfsad, dfsda1-0 bits of the block connecting th is port is ignored. when this bit is ?0?, dfsad, dfsda1-0 bits set the sampling speed mode. acskao: auto setting mode of porta output 0: disable, manual setting mode (default) 1: enable, auto setting mode master clock frequency is detected automatically at acksao bit ?1?. in this case, the setting of dfsad, dfsda1-0 bits of the block connecting th is port is ignored. when this bit is ?0?, dfsad, dfsda1-0 bits set the sampling speed mode. acskai: auto setting mode of porta input 0: disable, manual setting mode (default) 1: enable, auto setting mode master clock frequency is detected automatically at acksai bit ?1?. in this case, the setting of dfsad, dfsda1-0 bits of the block connecting th is port is ignored. when this bit is ?0?, dfsad, dfsda1-0 bits set the sampling speed mode. [ak4683] ms0427-e-02 2007/04 - 70 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 07h data source select 1 0 0 ditd1 ditd0 sdtob1 sdtob0 sdtoa1 sdtoa0 default 0 0 1 1 0 1 0 1 sdtoa1-0: data source control for porta 00: dir 01: adc (default) 10: sdtib 11: off (?l? output) sdtob1-0: data source control for portb 00: dir 01: adc (default) 10: off (?l? output) 11: sdtia1 ditd1-0: data source control for dit 00: dir 01: adc 10: sdtib 11: sdtia1 (default) [ak4683] ms0427-e-02 2007/04 - 71 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 08h data source select 2 0 dac22 dac21 dac20 0 dac12 dac11 dac10 default 0 1 0 0 0 0 1 1 dac12-10: data source control for dac1 000: dir 001: adc 010: sdtib 011: sdtia1 (default) 100: sdtia2 101: sdtia3 dac22-20: data source control for dac2 000: dir 001: adc 010: sdtib 011: sdtia1 100: sdtia2 (default) 101: sdtia3 addr register name d7 d6 d5 d4 d3 d2 d1 d0 09h analog input control 0 0 0 0 0 ain2 ain1 ain0 default 0 0 0 0 0 0 0 0 ain2-0: adc input selector control 000: lin1/rin1 (default) 001: lin2/rin2 010: lin3/rin3 011: lin4/rin4 100: lin5/rin5 101: lin6/rin6 110: none 111: none addr register name d7 d6 d5 d4 d3 d2 d1 d0 0ah audio data format 0 0 difb1 difb0 tdma1 tdma0 difa1 difa0 default 0 0 1 0 0 0 1 0 difa1-0, tdma1-0: audio format control for porta refer table 31, table 32, table 33. difb1-0: audio format control for portb refer table 34. addr register name d7 d6 d5 d4 d3 d2 d1 d0 0bh de-emphasis/ att speed dem21 de m20 dem11 dem10 0 atsad 0 atsda default 0 1 0 1 0 0 0 0 atsda: dac digital attenuator transition time control atsad: adc digital attenuator transition time control refer table 37, table 38. dem11-10: dac1 de-emphasis filter control dem21-20: dac2 de-emphasis filter control refer table 30. default: ?01?, off [ak4683] ms0427-e-02 2007/04 - 72 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 0ch lin volume control attad7 attad6 attad5 attad4 attad3 attad2 attad1 attad0 0dh rin volume control attad7 attad6 attad5 attad4 attad3 attad2 attad1 attad0 default 0 0 1 1 0 0 0 0 attad7-0: adc attenuation level control refer table 35. default: ?30h?, 0bd addr register name d7 d6 d5 d4 d3 d2 d1 d0 0eh lout1 volume control attda7 attda6 attda5 attda4 attda3 attda2 attda1 attda0 0fh rout1 volume control attda7 attda6 attda5 attda4 attda3 attda2 attda1 attda0 10h lout2 volume control attda7 attda6 attda5 attda4 attda3 attda2 attda1 attda0 11h rout2 volume control attda7 attda6 attda5 attda4 attda3 attda2 attda1 attda0 default 0 0 0 1 1 0 0 0 attda7-0: dac attenuation level control refer table 36. default: ?18h?, 0db addr register name d7 d6 d5 d4 d3 d2 d1 d0 12h hp volume control 0 0 0 opga4 opga3 opga2 opga1 opga0 default 0 0 0 0 0 0 0 0 opga5-0: hp opga attenuation level control refer table 42. default: ?00h?, mute addr register name d7 d6 d5 d4 d3 d2 d1 d0 13h ovf/dzf/v control 0 0 zce vin func1 func0 dzfm1 dzfm0 default 0 0 1 0 0 0 0 0 dzfm1-0: dzf mode setting refer table 7. func1-0: ovf/dzf/v mode control 00: off (?l? output. default) 01: adc overflow detection 10: dac zero data detection 11: v output vin: dit v bit control 0: v bit = ?0? (default) 1: v bit = ?1? zce: opga zero-cross enable 0: disable 1: enable (default) [ak4683] ms0427-e-02 2007/04 - 73 - register map (dir/dit part) addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h clk & power down control cs12 1 cm1 cm0 ocks1 ocks0 pwn rstn2 01h format & de-em control 0 1 1 0 deau dem1 dem0 dfs 02h input/ output control 0 txe 0 ops1 ops0 0 0 0 0 03h input/ output control 1 efh1 efh0 0 0 dit 0 ips1 ips0 04h int mask mqit0 maut0 mcit0 mulk0 mdts0 mpe0 maud0 mpar0 05h test 1 0 1 1 0 1 0 1 06h receiver status 0 qint aut o cint unlck dtscd pem audion par 07h receiver status 1 fs3 fs2 fs1 fs0 0 v qcrc ccrc 08h rx channel status byte 0 cr7 cr6 cr5 cr4 cr3 cr2 cr1 cr0 09h rx channel status byte 1 cr15 cr14 cr13 cr12 cr11 cr10 cr9 cr8 0ah rx channel status byte 2 cr23 cr22 cr21 cr20 cr19 cr18 cr17 cr16 0bh rx channel status byte 3 cr31 cr30 cr29 cr28 cr27 cr26 cr25 cr24 0ch rx channel status byte 4 cr39 cr38 cr37 cr36 cr35 cr34 cr33 cr32 0dh tx channel status byte 0 ct7 ct6 ct5 ct4 ct3 ct2 ct1 ct0 0eh tx channel status byte 1 ct15 ct14 ct13 ct12 ct11 ct10 ct9 ct8 0fh tx channel status byte 2 ct23 ct22 ct21 ct20 ct19 ct18 ct17 ct16 10h tx channel status byte 3 ct31 ct30 ct29 ct28 ct27 ct26 ct25 ct24 11h tx channel status byte 4 ct39 ct39 ct39 ct39 ct39 ct39 ct39 ct32 12h burst preamble pc byte 0 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 13h burst preamble pc byte 1 pc15 pc14 pc13 pc12 pc11 pc10 pc9 pc8 14h burst preamble pd byte 0 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 15h burst preamble pd byte 1 pd15 pd14 pd13 pd12 pd11 pd10 pd9 pd8 16h q-subcode address / control q9 q8 q7 q6 q5 q4 q3 q2 17h q-subcode track q17 q16 q15 q14 q13 q12 q11 q10 18h q-subcode index q25 q24 q23 q22 q21 q20 q19 q18 19h q-subcode minute q33 q32 q31 q30 q29 q28 q27 q26 1ah q-subcode second q41 q40 q39 q38 q37 q36 q35 q34 1bh q-subcode frame q49 q48 q47 q46 q45 q44 q43 q42 1ch q-subcode zero q57 q56 q55 q54 q53 q52 q51 q50 1dh q-subcode abs minute q65 q64 q63 q62 q61 q60 q59 q58 1eh q-subcode abs second q73 q72 q71 q70 q69 q68 q67 q66 1fh q-subcode abs frame q81 q80 q79 q78 q77 q76 q75 q74 when pdn pin goes ?l?, the registers ar e initialized to their default values. when rstn bit goes ?0?, the internal timing is reset an d the registers are initialized to their default values. all data can be written to the register even if pwn bit is ?0?. the ?0? register should be written ?0?, th e ?1? register should be written ?1? data. [ak4683] ms0427-e-02 2007/04 - 74 - register definitions reset & initialize addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h clk & power down control cs12 1 cm1 cm0 ocks1 ocks0 pwn rstn2 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 1 0 0 0 0 1 1 rstn2: timing reset & register initialize 0: reset & initialize 1: normal operation (default) pwn: power down 0: power down 1: normal operation (default) ocks1-0: master clock frequency select refer table 3, table 57. cm1-0: master clock operation mode select refer table 1, table 45, table 55. cs12: channel status select 0: channel 1 (default) 1: channel 2 selects which channel status is used to derive c-bit buffers, audion, pem, fs3, fs2, fs1, fs0, pc and pd. the de-emphasis filter is controlled by channel 1 in the parallel mode. format & de-emphasis control addr register name d7 d6 d5 d4 d3 d2 d1 d0 01h format & de-em control 0 1 1 0 deau dem1 dem0 dfs r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 1 1 0 1 0 1 0 dfs: 96khz de-emphasis control refer table 52. dem1-0: 32, 44.1, 48khz de-emphasis control refer table 52. deau: de-emphasis auto detect enable 0: disable 1: enable (default) [ak4683] ms0427-e-02 2007/04 - 75 - input/output control addr register name d7 d6 d5 d4 d3 d2 d1 d0 02h input/ output control 0 txe 0 ops1 ops0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 1 0 0 0 0 0 0 0 ops1-0: output through data select for tx pin refer table 54. txe: tx output enable 0: disable. tx0 pin outputs ?l?. 1: enable (default) addr register name d7 d6 d5 d4 d3 d2 d1 d0 03h input/ output control 1 efh1 efh0 0 0 dit 0 ips1 ips0 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 1 0 0 1 0 0 0 ips1-0: input recovery data select refer table 53. dit: through data/transmit data select for tx1 pin 0: through data (rx data). 1: transmit data (daux2 data. default.). (u bit for dit is fixed to ?0?) efh1-0: interrupt 0 pin hold count select 00: 512 lrck2 01: 1024 lrck (default) 10: 2048 lrck 11: 4096 lrck mask control for int addr register name d7 d6 d5 d4 d3 d2 d1 d0 04h int mask mqi0 mat0 mci0 mul0 mdts0 mpe0 man0 mpr0 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 1 1 1 0 1 1 1 0 mpr0: mask enable for par bit man0: mask enable for audn bit mpe0: mask enable for pem bit mdts0: mask enable for dtscd bit mul0: mask enable for unlock bit mci0: mask enable for cint bit mat0: mask enable for auto bit mqi0: mask enable for qint bit 0: mask disable 1: mask enable [ak4683] ms0427-e-02 2007/04 - 76 - receiver status 0 addr register name d7 d6 d5 d4 d3 d2 d1 d0 06h receiver status 0 qint auto c int unlck dtscd pem audion par r/w rd rd rd rd rd rd rd rd default 0 0 0 0 0 0 0 0 par: parity error or biphase error status 0: no error 1: error it is ?1? if parity error or biphase error is detected in the sub-frame. audion: audio bit output 0: audio 1: non audio this bit is made by encoding channel status bits. pem: pre-emphasis detect. 0: off 1: on this bit is made by encoding channel status bits. dtscd: dts-cd auto detect 0: no detect 1: detect unlck: pll lock status 0: locked 1: unlocked cint: channel status buffer interrupt 0: no change 1: changed auto: non-pcm auto detect 0: no detect 1: detect qint: q-subcode buffer interrupt 0: no change 1: changed qint, cint and par bits are initialized when 06h is read. [ak4683] ms0427-e-02 2007/04 - 77 - receiver status 1 addr register name d7 d6 d5 d4 d3 d2 d1 d0 07h receiver status 1 fs3 fs2 fs1 fs0 0 v qcrc ccrc r/w rd rd rd rd rd rd rd rd default 0 0 0 1 0 0 0 0 ccrc: cyclic redundancy check for channel status 0:no error 1:error qcrc: cyclic redundancy check for q-subcode 0:no error 1:error v: validity of channel status 0:valid 1: invalid fs3-0: sampling frequency detection (refer table 48.) [ak4683] ms0427-e-02 2007/04 - 78 - receiver channel status addr register name d7 d6 d5 d4 d3 d2 d1 d0 08h rx channel status byte 0 cr7 cr6 cr5 cr4 cr3 cr2 cr1 cr0 09h rx channel status byte 1 cr15 cr14 cr13 cr12 cr11 cr10 cr9 cr8 0ah rx channel status byte 2 cr23 cr22 cr21 cr20 cr19 cr18 cr17 cr16 0bh rx channel status byte 3 cr31 cr30 cr29 cr28 cr27 cr26 cr25 cr24 0ch rx channel status byte 4 cr39 cr38 cr37 cr36 cr35 cr34 cr33 cr32 r/w rd default not initialized cr39-0: receiver channel status byte 4-0 transmitter channel status addr register name d7 d6 d5 d4 d3 d2 d1 d0 0dh tx channel status byte 0 ct7 ct6 ct5 ct4 ct3 ct2 ct1 ct0 0eh tx channel status byte 1 ct15 ct14 ct13 ct12 ct11 ct10 ct9 ct8 0fh tx channel status byte 2 ct23 ct22 ct21 ct20 ct19 ct18 ct17 ct16 10h tx channel status byte 3 ct31 ct30 ct29 ct28 ct27 ct26 ct25 ct24 11h tx channel status byte 3 ct39 ct38 ct37 ct36 ct35 ct34 ct335 ct32 r/w r/w default 0 ct39-0: transmitter channel status byte 4-0 [ak4683] ms0427-e-02 2007/04 - 79 - burst preamble pc/pd in non-pcm encoded audio bitstreams addr register name d7 d6 d5 d4 d3 d2 d1 d0 12h burst preamble pc byte 0 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 13h burst preamble pc byte 1 pc15 pc14 pc13 pc12 pc11 pc10 pc9 pc8 14h burst preamble pd byte 0 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 15h burst preamble pd byte 1 pd15 pd14 pd13 pd12 pd11 pd10 pd9 pd8 r/w rd default not initialized pc15-0: burst preamble pc byte 0 and 1 pd15-0: burst preamble pd byte 0 and 1 q-subcode buffer addr register name d7 d6 d5 d4 d3 d2 d1 d0 16h q-subcode address / control q9 q8 q7 q6 q5 q4 q3 q2 17h q-subcode track q17 q16 q15 q14 q13 q12 q11 q10 18h q-subcode index q25 q24 q23 q22 q21 q20 q19 q18 19h q-subcode minute q33 q32 q31 q30 q29 q28 q27 q26 1ah q-subcode second q41 q40 q39 q38 q37 q36 q35 q34 1bh q-subcode frame q49 q48 q47 q46 q45 q44 q43 q42 1ch q-subcode zero q57 q56 q55 q54 q53 q52 q51 q50 1dh q-subcode abs minute q65 q64 q63 q62 q61 q60 q59 q58 1eh q-subcode abs second q73 q72 q71 q70 q69 q68 q67 q66 1fh q-subcode abs frame q81 q80 q79 q78 q77 q76 q75 q74 r/w rd default not initialized [ak4683] ms0427-e-02 2007/04 - 80 - system design figure 50 shows the system connection diagram. the evaluation board is available which demonstrates application circuits, the optimum layout, power supply arrangements and measurement results. ak4683 + 10u 0.1u a nalog 5v a nalog ground digital ground micro controller 5 + 2.2u 0.1u 12k x?tal cc mute 3.3v to 5 v digital audio dsp2 audio dsp1 mute pvdd 1 rx0 2 i2c 3 rx1 4 rx2 5 rx3 6 int 7 dzf 8 cdto/test 9 lrckb 10 bickb 11 sdtob 12 olrcka 13 ilrcka 14 bicka 15 sdtoa 16 64 r pvss rin 6 lin 6 rin 5 lin 5 rin4 lin4 rin 3 lin 3 rin2 lin2 rin1 lin1 avdd1 17 mcko 18 tvdd dvss dvdd xti xto tx mclk2 pdn sda scl csn/test sdtia sdtia sdtia3 sdtib rise l 48 ropin 47 lopin 46 lise l 45 avss2 44 avdd2 43 vcom 42 rout2 41 lout2 40 rout2 39 lout2 38 mutet 37 hp l 36 hp r 35 hvss 34 hvdd 33 avss1 19 20 21 22 23 24 25 26 27 28 29 30 31 32 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 + 10u 0.1u + 10u 0.1u mute mute + 10u 0.1u + 10u 0.1u 5v digital s/pdif out 1u 6.8 47u 6.8 47u a nalog 5v + 10u 0.1u headphone analog in analog ou t s/pdif sources figure 50. typical connection diagram( i 2 c serial control mode) notes: - ?c? depends on the crystal. - avss, dvss, pvss and hvss must be co nnected to the same analog ground plane. - digital signals, especially clocks, should be kept away from the r pin in order to avoid an effect to the clock jitter performance. - in case of coaxial input, ground of rca connector and terminator should be connected to pvss of the ak4683 with low impedance on pc board. [ak4683] ms0427-e-02 2007/04 - 81 - 1. grounding and power supply decoupling the ak4683 requires careful attention to power supply and grounding arrangements. avdd1, avdd2, dvdd, pvdd and hvdd are usually supplied from analog supply in system. if avdd1, avdd2, dvdd, pvdd and hvdd are supplied separately, the power up sequence is not critical. avss1, avss2, dvss pvss and hvss of the ak4683 must be connected to analog ground plane. system analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board. decoupling capacitors should be as near to the ak4683 as possible, with the small va lue ceramic capacitor being the nearest. 2. voltage reference inputs the voltage of avdd1, avdd2 sets the analog input/output range. vcom is a signal ground of this chip. an electrolytic capacitor 2.2 f parallel with a 0.1 f ceramic capacitor attached be tween vcom pin and avss1 pin eliminates the effects of high frequency noise. no load current may be drawn from vcom pin. all signals, especially clocks, should be kept away from the avdd1, avdd2 and vcom pins in order to avoid unwanted coupling into the ak4683. 3. analog inputs the ak4683 receives the analog input through the single-ended pre-amp usin g external resistors. adjust the input level/gain at pre-amp to match the input range 1.22 x avdd1 vpp (typ. fs=48khz, ri =47kohm, rf = 24kohm). each input pins are biased internally. the adc output data form at is 2?s complement. the internal digital hpf removes the dc offset. the ak4683 samples the analog inputs at 64fs. the digital filter rejects noise above the stop band except for multiples of 64fs. the ak4683 includes an anti-aliasing f ilter (rc filter) to attenuate a noise around 64fs. 4. analog outputs the analog outputs are also single-ended and centered around the vcom voltage. the input signal range scales with the supply voltage and nominally 0.6 x avdd2 vpp. the dac input data format is 2?s complement. the output voltage is a positive full scale for 7fffffh(@24bit) and a negative fu ll scale for 800000h(@24bit). the ideal output is vcom voltage for 000000h(@24bit). the internal analog filters remove most of the noise generated by the delta-sigma modulator of dac beyond the audio passband. dc offsets on analog outputs are eliminated by ac coupling since dac outputs have dc offsets of a few mv. 5. attention to the pcb wiring lin1-6 and rin1-6 pins are the summing nodes of the pre-amp. attention should be given to avoid coupling with other signals on those nodes. this can be accomplished by making the wire length of the input resistors as short as possible. the same theory also applies to the lopin/ropin pins and feedback resistors; keep the wire length to a minimum. unused input pins among lin1-6 and rin1-6 pins should be left open. [ak4683] ms0427-e-02 2007/04 - 82 - package package & lead frame material package molding compound: epoxy lead frame material: cu lead frame surface treatment: solder (pb free) plate 12.00.3 0.210.05 0.170.05 12.00.3 1 16 17 32 33 48 49 64 0.10 0.5 1.70max 0.100.10 0 ~10 0.450.2 10.0 64pin lqfp(unit:mm) 1.40 0.10 m 1.0 [ak4683] ms0427-e-02 2007/04 - 83 - marking 1 akm ak4683eq xxxxxxx 1) pin #1 indication 2) asahi kasei logo 3) marking code: ak4683eq 4) date code: xxxxxxx(7 digits) revision history date (yy/mm/dd) revision reason page contents 05/09/30 00 first edition 05/11/15 01 error correction 30 table 28, 29: ?off? -> ?sdtib? 38 ?(table 16)? -> ?(table 37, table 38)? 67 clkdt: ?table 58? -> ?table 56? selao: ?dit[1:0]? -> ?ditd[1:0]? 07/4/1 02 comment addition 23,25 notes were added for the synchronous operation of porta and portb. [ak4683] ms0427-e-02 2007/04 - 84 - important notice ? these products and their specifications are subject to change without notice. before considering any use or application, consult the asahi kasei emd corporation (emd) sales office or authorized distributor concerning their current status. ? emd assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. ? any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of th e country of export pertaining to customs and tariffs, currency exchange, or strategic materials. ? emd products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and emd assumes no responsibility relating to any such use, except with the express written consent of the re presentative director of emd. as used here: a. a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. b. a critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. ? it is the responsibility of the buyer or distributor of an emd product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assu me any and all responsibility and liability for and hold emd harmless from any and all claims arising from th e use of said product in the absence of such notification. |
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